LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 840

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
36.7.2.4.2 Loop-back mode
36.7.2.4.3 Loop-back mode combined with Silent mode
The CAN Core can be set in Loop-back mode by programming the Test Register bit
LBACK to one. In Loop-back Mode, the CAN Core treats its own transmitted messages as
received messages and stores them (if they pass acceptance filtering) into a Receive
Buffer.
This mode is provided for self-test functions. To be independent from external stimulation,
the CAN Core ignores acknowledge errors (recessive bit sampled in the acknowledge slot
of a data/remote frame) in Loop-back mode. In this mode the CAN core performs an
internal feedback from its CAN_TXD output to its CAN_RXD input. The actual value of the
CAN_RXD input pin is disregarded by the CAN Core. The transmitted messages can be
monitored at the CAN_TXD pin.
It is also possible to combine Loop-back mode and Silent mode by programming bits
LBACK and SILENT to one at the same time. This mode can be used for a “Hot Selftest”,
meaning the C_CAN can be tested without affecting a running CAN system connected to
the pins CAN_TXD and CAN_RXD. In this mode the CAN_RXD pin is disconnected from
the CAN Core and the CAN_TXD pin is held recessive.
Fig 125. CAN core in Silent mode
Fig 126. CAN core in Loop-back mode
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
C_CAN
C_CAN
TD0, TD1 RD0, RD1
TD0, TD1 RD0, RD1
= 1
Rx
Rx
CAN CORE
CAN CORE
Tx
Tx
Chapter 36: LPC18xx C_CAN
UM10430
© NXP B.V. 2011. All rights reserved.
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