LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 505

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 428. DMA operation mode register (DMA_OP_MODE, address 0x4001 1018) bit description
Table 429. DMA Interrupt enable register (DMA_INT_EN, address 0x4001 101C) bit description
<Document ID>
User manual
Bit
24
25
26
31:27
Bit
0
1
2
3
4
5
Symbol
DFF
RSF
DT
-
Symbol
TIE
TSE
TUE
TJE
OVE
UNE
22.6.24 DMA Interrupt enable register
Description
Disable flushing of received frames
When this bit is set, the RxDMA does not flush any frames due to the unavailability of
receive descriptors/buffers as it does normally when this bit is reset. (See ).
Receive store and forward
When this bit is set, the MTL only reads a frame from the Rx FIFO after the complete
frame has been written to it, ignoring RTC bits. When this bit is reset, the Rx FIFO
operates in Cut-Through mode, subject to the threshold specified by the RTC bits.
Disable Dropping of TCP/IP Checksum Error Frames
When this bit is set, the core does not drop frames that only have errors detected by
the Receive Checksum Offload engine. Such frames do not have any errors
(including FCS error) in the Ethernet frame received by the MAC but have errors in
the encapsulated payload only. When this bit is reset, all error frames are dropped if
the FEF bit is reset.
Reserved
Description
Transmit interrupt enable
When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register),
Transmit Interrupt is enabled. When this bit is reset, Transmit Interrupt is disabled.
Transmit stopped enable
When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register),
Transmission Stopped Interrupt is enabled. When this bit is reset, Transmission
Stopped Interrupt is disabled.
Transmit buffer unavailable enable
When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register),
Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, Transmit
Buffer Unavailable Interrupt is disabled.
Transmit jabber timeout enable
When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register),
Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, Transmit Jabber
Timeout Interrupt is disabled.
Overflow interrupt enable
When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register),
Receive Overflow Interrupt is enabled. When this bit is reset, Overflow Interrupt is
disabled.
Underflow interrupt enable
When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register),
Transmit Underflow Interrupt is enabled. When this bit is reset, Underflow Interrupt is
disabled.
The Interrupt Enable register enables the interrupts reported by the DMA_STAT register.
Setting a bit to 1 enables a corresponding interrupt. After a hardware or software reset, all
interrupts are disabled.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 22: LPC18xx Ethernet
UM10430
© NXP B.V. 2011. All rights reserved.
…continued
Reset
value
0
0
0
0
Reset
value
0
0
0
0
0
0
505 of 1164
Access
R/W
R/W
R/W
RO
Access
R/W
R/W
R/W
R/W
R/W
R/W