LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 24

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
3.3.1 AES capable devices
3.3.2 Boot process
AES capable products will normally always boot from a secure (encrypted) image and use
CMAC authentication. However a special development mode allows booting from a plain
text image. This development mode is active when the AES key has not been
programmed. In this case the AES key consists of all zeros. Once the key is programmed
(to a non-zero value), the development mode is terminated.
The top level boot process is illustrated in
released. The IRC is selected as CPU clock and the Cortex-M3 starts by executing boot
ROM. By default the JTAG access to the chip is disabled at reset. When the part is
non-AES capable or it is AES capable but the AES key has not been programmed then
JTAG access is enabled.
As shown in
BOOT_SRC value or reset state of the pins P1_1, P1_2, P2_8, and P2_9. The boot ROM
copies the image to internal SRAM at location 0x1000 0000 and jumps to that location
(sets ARM's shadow pointer to 0x1000 0000) after image verification. Hence the images
for LPC18xx should be compiled with entry point at 0x0000 0000. On AES capable
LPC18xx with a programmed AES key the image and header are authenticated using the
CMAC algorithm. If authentication fails the device is reset.
On AES capable LPC18xx in development mode and non-AES capable LPC18xx, the
image and header are not authenticated. If the image is not preceded by a header then
the image is not copied to SRAM but assumed to be executable as-is. In that case the
shadow pointer is set to the first address location of the external boot memory. The
header-less images for LPC18xx should be compiled with entry point at 0x0000 0000, the
same as for an image with header.
Figure
All information provided in this document is subject to legal disclaimers.
9, the boot ROM determines the boot mode based on the OTP
Rev. 00.13 — 20 July 2011
Figure
9. The boot starts after Reset is
Chapter 3: LPC18xx Boot ROM
UM10430
© NXP B.V. 2011. All rights reserved.
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