LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 264

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
16.4 General description
16.5 DMA system connections
<Document ID>
User manual
The DMA controller allows peripheral-to memory, memory-to-peripheral,
peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream
provides unidirectional serial DMA transfers for a single source and destination. For
example, a bi-directional port requires one stream for transmit and one for receives. The
source and destination areas can each be either a memory region or a peripheral for
master 1, but only memory for master 0.
The connection of the DMA Controller to supported peripheral devices is shown in
Table
connect peripherals to the DMA. The DMAMUX register in the CREG block controls which
option is used (see
Table 195. Peripheral connections to the DMA controller and matching flow control signals
Peripheral
Number
0
1
2
3
•
•
•
•
Supports 8, 16, and 32-bit wide transactions.
Big-endian and little-endian support. The DMA Controller defaults to little-endian
mode on reset.
An interrupt to the processor can be generated on a DMA completion or when a DMA
error has occurred.
Raw interrupt status. The DMA error and DMA count raw interrupt status can be read
prior to masking.
195. The LPC18xx supports up to three different muxing options for each channel to
DMA
muxing
option
(see
Table
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
All information provided in this document is subject to legal disclaimers.
35)
Table
Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller
Rev. 00.13 — 20 July 2011
SREQ
SPIFI
SCT match 2<tbd>
Reserved
Timer 3 match 1
n.c.
n.c.
Reserved
n.c.
n.c.
n.c.
Reserved
n.c.
n.c.
n.c.
n.c.
SSP1 transmit
35).
BREQ
SPIFI
Reserved
Timer 0 match 0
USART0 transmit
Reserved
AES input
Timer 0 match 1
USART0 receive
Reserved
AES output
Timer 1 match 0
UART1 transmit
I2S1 channel 0
SSP1 transmit
UM10430
© NXP B.V. 2011. All rights reserved.
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