LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 258

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
15.5.3.2 GPIO port word pin registers
15.5.3.3 GPIO port direction registers
15.5.3.4 GPIO port mask registers
Each GPIO pin GPIOn[m] has a word register in this address range. The word pin
registers of GPIO port 0 correspond to registers W0 to W31, the word pin registers of
GPIO port 1 correspond to registers W32 to W63, etc.. Word addresses are reserved for
unused GPIO port pins (see
Any byte, halfword, or word read in this range will be all zeros if the pin is low or all ones if
the pin is high, regardless of direction, masking, or alternate function, except that pins
configured as analog I/O always read as zeros. Any write will clear the pin’s output bit if
the value written is all zeros, else it will set the pin’s output bit.
Table 185. GPIO port word pin registers (W, addresses 0x400F 5000 (W0) to 0x400F 13FC
Each GPIO port n (n = 0 to 7) has one direction register for configuring the port pins as
inputs or outputs.
Table 186. GPIO port direction register (DIR, addresses 0x400F 6000 (DIR0) to 0x400F 601C
Each GPIO port has one mask register. The mask registers affect writing and reading the
MPORT registers. Zeroes in these registers enable reading and writing; ones disable
writing and result in zeros in corresponding positions when reading.
Table 187. GPIO port mask register (MASK, addresses 0x400F 6080 (MASK0) to 0x400F 609C
Bit
31:0
Bit
31:0
Bit
31:0 MASK
Symbol
Symbol
DIR
Symbol
PWORD Read 0: pin GPIOn[m] is LOW.
(W255)) bit description
(DIR7)) bit description
(MASK7)) bit description
All information provided in this document is subject to legal disclaimers.
Description
Controls which bits corresponding to GPIOn[m] are active in
the MPORT register (bit 0 = GPIOn[0], bit 1 = GPIOn[1], ..., bit
31 = GPIOn[31]).
0 = Read MPORT: pin state; write MPORT: load output bit.
1 = Read MPORT: 0; write MPORT: output bit not affected.
Description
Write 0: clear output bit.
Read 0xFFFF FFFF: pin is HIGH.
Write any value 0x0000 0001 to 0xFFFF FFFF: set output
bit.
Remark: Only 0 or 0xFFFF FFFF can be read. Writing any
value other than 0 will set the output bit.
Description
Selects pin direction for pin GPIOn[m] (bit 0 = GPIOn[0], bit
1 = GPIOn[1], ..., bit 31 = GPIOn[31]).
0 = input.
1 = output.
Rev. 00.13 — 20 July 2011
Table
165).
Chapter 15: LPC18xx GPIO
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
ext
Reset
value
0
Reset
value
0
258 of 1164
Access
R/W
Access
R/W
Access
R/W