LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 344

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
19.7.26 Static Memory Write Delay registers
19.7.27 Static Memory Turn Round Delay registers
Table 291. Static Memory Page Mode Read Delay registers (STATICWAITPAGE, address
The StaticWaitWr registers enable you to program the delay from the chip select to the
write access. It is recommended that these registers are modified during system
initialization, or when there are no current or outstanding transactions. This can be
ensured by waiting until the EMC is idle, and then entering low-power, or disabled
mode.These registers are not used if the extended wait (EW) bit is enabled in the
StaticConfig register. These registers are accessed with one wait state.
Table 292. Static Memory Write Delay registers (STATICWAITWR, address 0x4000 5214
The StaticWaitTurn registers enable you to program the number of bus turnaround cycles.
It is recommended that these registers are modified during system initialization, or when
there are no current or outstanding transactions. This can be ensured by waiting until the
EMC is idle, and then entering low-power, or disabled mode. These registers are
accessed with one wait state.
Bit
4:0
31:5
Bit
4:0
31:5
Symbol
WAITWR Write wait states.
Symbol
WAITPAGE Asynchronous page mode read after the first read wait states.
-
-
0x4000 5210 (STATICWAITPAGE0), 0x4000 5230 (STATICWAITPAGE1),
0x4000 5250 (STATICWAITPAGE2), 0x4000 5270 (STATICWAITPAGE3)) bit
description
(STATICWAITWR0), 0x4000 5234 (STATICWAITWR1), 0x4000 5254
(STATICWAITWR2), 0x4000 5274 (STATICWAITWR3)) bit description
All information provided in this document is subject to legal disclaimers.
Description
SRAM wait state time for write accesses after the first read:
0x0 - 0x1E = (n + 2) CCLK cycle write access time. The wait state time
for write accesses after the first read is WAITWR (n + 2) x tCCLK.
0x1F = 33 CCLK cycle write access time (POR reset value).
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Description
Number of wait states for asynchronous page mode read accesses
after the first read:
0x0 - 0x1E = (n+ 1) CCLK cycle read access time. For asynchronous
page mode read for sequential reads, the wait state time for page
mode accesses after the first read is (WAITPAGE + 1) x tCCLK.
0x1F = 32 CCLK cycle read access time (POR reset value).
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Rev. 00.13 — 20 July 2011
Chapter 19: LPC18xx External Memory Controller (EMC)
UM10430
© NXP B.V. 2011. All rights reserved.
344 of 1164
Reset
value
0x1F
-
Reset
value
0x1F
-