LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 775

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
34.6.4 SSP Status Register
34.6.5 SSP Clock Prescale Register
34.6.6 SSP Interrupt Mask Set/Clear Register
This read-only register reflects the current status of the SSP controller.
Table 719: SSP Status Register (SR - address 0x4008 300C (SSP0), 0x400C 500C (SSP1)) bit
This register controls the factor by which the Prescaler divides the SSP peripheral clock
PCLK to yield the prescaler clock that is, in turn, divided by the SCR factor in SSPnCR0,
to determine the bit clock.
Table 720: SSP Clock Prescale Register (CPSR - address 0x4008 3010 (SSP0), 0x400C 5010
Important: the SSPnCPSR value must be properly initialized or the SSP controller will not
be able to transmit data correctly.
In Slave mode, the SSP clock rate provided by the master must not exceed 1/12 of the
SSP peripheral clock. The content of the SSPnCPSR register is not relevant.
In master mode, CPSDVSR
This register controls whether each of the four possible interrupt conditions in the SSP
controller are enabled. Note that ARM uses the word “masked” in the opposite sense from
classic computer terminology, in which “masked” meant “disabled”. ARM uses the word
“masked” to mean “enabled”. To avoid confusion we will not use the word “masked”.
Bit
0
1
2
3
4
31:5
Bit
7:0
31:8
Symbol
CPSDVSR
-
Symbol Description
TFE
TNF
RNE
RFF
BSY
-
description
(SSP1)) bit description
All information provided in this document is subject to legal disclaimers.
Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not. 1
Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not.
Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if
not.
Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not.
Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently
sending/receiving a frame and/or the Tx FIFO is not empty.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Description
This even value between 2 and 254, by which PCLK is divided to yield
the prescaler output clock. Bit 0 always reads as 0.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Rev. 00.13 — 20 July 2011
min
= 2 or larger (even numbers only).
Chapter 34: LPC18xx SSP0/1
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0
0
NA
Reset
value
0
NA
1
0