LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 418

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
20.10.5.3.1 Data toggle reset
20.10.5.3.2 Data toggle inhibit
20.10.5.2 Stalling
20.10.5.3 Data toggle
There are two occasions where the device controller may need to return to the host a
STALL:
Remark: Any write to the ENDPTCTRLx register during operational mode must preserve
the endpoint type field (i.e. perform a read-modify-write).
Table 348. Device controller stall response matrix
Data toggle is a mechanism to maintain data coherency between host and device for any
given data pipe. For more information on data toggle, refer to the USB 2.0 specification.
The DCD may reset the data toggle state bit and cause the data toggle sequence to reset
in the device controller by writing a ‘1’ to the data toggle reset bit in the ENDPTCTRLx
register. This should only be necessary when configuring/initializing an endpoint or
returning from a STALL condition.
Remark: This feature is for test purposes only and should never be used during normal
device controller operation.
USB packet
SETUP packet received by a non-control
endpoint.
IN/OUT/PING packet received by a
non-control endpoint.
IN/OUT/PING packet received by a
non-control endpoint.
SETUP packet received by a control endpoint. N/A
IN/OUT/PING packet received by a control
endpoint.
IN/OUT/PING packet received by a control
endpoint.
1. The first occasion is the functional stall, which is a condition set by the DCD as
2. A protocol stall, unlike a function stall, is used on control endpoints is automatically
described in the USB 2.0 device framework (chapter 9). A functional stall is only used
on non-control endpoints and can be enabled in the device controller by setting the
endpoint stall bit in the ENDPTCTRLx register associated with the given endpoint and
the given direction. In a functional stall condition, the device controller will continue to
return STALL responses to all transactions occurring on the respective endpoint and
direction until the endpoint stall bit is cleared by the DCD.
cleared by the device controller at the start of a new control transaction (setup phase).
When enabling a protocol stall, the DCD should enable the stall bits (both directions)
as a pair. A single write to the ENDPTCTRLx register can ensure that both stall bits
are set at the same instant.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
Endpoint
STALL bit
N/A
1
0
1
0
Effect on
STALL bit
None
None
None
Cleared
None
None
UM10430
© NXP B.V. 2011. All rights reserved.
USB response
STALL
STALL
ACK/NAK/NYET
ACK
STALL
ACK/NAK/NYET
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