LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 602

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 511. SCT bidirectional output control register (OUTPUTDIRCTRL - address 0x4000 0054) bit description
<Document ID>
User manual
Bit
25:
24
27:
26
29:
28
31:
30
Symbol
SETCLR12
SETCLR13
SETCLR14
SETCLR15
24.6.13 SCT conflict resolution register
Value Description
0x0
0x1
0x2
0x0
0x1
0x2
0x0
0x1
0x2
0x0
0x1
0x2
The registers OUTPUTSETn
both setting and clearing to be indicated for an output in the same clock cycle, even for the
same event. This SCT conflict resolution register controls what happens when this occurs.
To enable an event to toggle an output, set the OnRES value to 0x3 in this register, and
set the event’s bits in both the Set and Clear registers.
Table 512. SCT conflict resolution register (RES - address 0x4000 0058) bit description
Bit
1:0
3:2
Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value.
Set and clear do not depend on any counter.
Set and clear are reversed when counter L or the unified counter is counting down.
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value.
Set and clear do not depend on any counter.
Set and clear are reversed when counter L or the unified counter is counting down.
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value.
Set and clear do not depend on any counter.
Set and clear are reversed when counter L or the unified counter is counting down.
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value.
Set and clear do not depend on any counter.
Set and clear are reversed when counter L or the unified counter is counting down.
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
Symbol
O0RES
O1RES
All information provided in this document is subject to legal disclaimers.
Value Description
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
Rev. 00.13 — 20 July 2011
Effect of simultaneous set and clear on output 0.
No change.
Set output (or clear based on the SETCLR0 field).
Clear output (or set based on the SETCLR0 field).
Toggle output.
Effect of simultaneous set and clear on output 1.
No change.
Set output (or clear based on the SETCLR1 field).
Clear output (or set based on the SETCLR1 field).
Toggle output.
(Section
Chapter 24: LPC18xx State Configurable Timer (SCT)
24.6.25) and OUTPUTCLn
(Section
UM10430
© NXP B.V. 2011. All rights reserved.
24.6.26) allow
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Reset
value
0
0
0
0
Reset
value
0
0