LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 292

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
Fig 27. LLI example
0x2002 0000
0x2002 0010
0x2002 0020
0x2002 0070
16.8.5.1.2 Example of scatter/gather DMA
LLI1
LLI2
LLI3
LLI8
Source address
Destination address = peripheral
Next LLI address
Control information
Source address
Destination address = peripheral
Next LLI address
Control information
Source address
Destination address = peripheral
Next LLI address
Control information
Source address
Destination address = peripheral
Next LLI address
Control information
See
peripheral. The addresses of each LLI entry are given, in hexadecimal, at the left-hand
side of the figure. The right side of the figure shows the memory containing the data to be
transferred.
The first LLI, stored at 0x2002 0000, defines the first block of data to be transferred, which
is the data stored from address 0x2002 A200 to 0x2002 ADFF:
The second LLI, stored at 0x2002 0010, describes the next block of data to be transferred:
5. An interrupt can be generated at the end of each LLI depending on the Terminal
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•
•
•
•
•
•
•
Count bit in the CCONTROL Register. If this bit is set an interrupt is generated at the
end of the relevant LLI. The interrupt request must then be serviced and the relevant
bit in the INTTCCLEAR Register must be set to clear the interrupt.
Source start address 0x2002 A200.
Destination address set to the destination peripheral address.
Transfer width, word (32-bit).
Transfer size, 3072 bytes (0xC00).
Source and destination burst sizes, 16 transfers.
Next LLI address, 0x2002 0010.
Source start address 0x2002 B200.
Destination address set to the destination peripheral address.
Figure 27
Linked List Array
for an example of an LLI. A section of memory is to be transferred to a
All information provided in this document is subject to legal disclaimers.
= 0x 2002 A200
= 0x2002 0010
= length 3072
= 0x 2002 B200
= 0x2002 0020
= length 3072
= 0x 2002 C200
= 0x2002 0030
= length 3072
= 0x 2003 1200
= 0 (end of list)
= length 3072
Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller
Rev. 00.13 — 20 July 2011
0x2002 CDFF
0x2002 ADFF
0x2002 BDFF
0x2003 1DFF
0x2002 C200
0x2002 A200
0x2002 B200
0x2003 1200
3072 bytes of data
3072 bytes of data
3072 bytes of data
3072 bytes of data
UM10430
© NXP B.V. 2011. All rights reserved.
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