LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 457

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 383. USB Transfer buffer Fill Tuning register in host mode (TXFILLTUNING - address 0x4000 7164) bit
<Document ID>
User manual
Bit
7:0
12:8
15:13 -
21:16 TXFIFOTHRES
31:22 -
Symbol
TXSCHOH
TXSCHEATLTH Scheduler health counter
description
21.6.11 USB ULPI viewport register (ULPIVIEWPORT)
Upon discovery of a transmit (OUT/SETUP) packet in the data structures, host controller
checks to ensure T
pre-fill the TX FIFO. If at anytime during the pre-fill operation the time remaining the
[micro]frame is < T
Although this is not an error condition and the host controller will eventually recover, a
mark will be made the scheduler health counter to note the occurrence of a “backoff”
event. When a back-off event is detected, the partial packet fetched may need to be
discarded from the latency buffer to make room for periodic traffic that will begin after the
next SOF. Too many back-off events can waste bandwidth and power on the system bus
and thus should be minimized (not necessarily eliminated). Backoffs can be minimized
with use of the TSCHHEALTH (T
The register provides indirect access to the ULPI PHY register set. Although the core
performs access to the ULPI PHY register set, there may be extraordinary circumstances
where software may need direct access.
Description
FIFO burst threshold
This register controls the number of data bursts that are posted to the TX
latency FIFO in host mode before the packet begins on to the bus. The
minimum value is 2 and this value should be a low as possible to maximize
USB performance. A higher value can be used in systems with unpredictable
latency and/or insufficient bandwidth where the FIFO may underrun because
the data transferred from the latency FIFO to USB occurs before it can be
replenished from system memory. This value is ignored if the Stream Disable
bit in USBMODE register is set.
This register increments when the host controller fails to fill the TX latency
FIFO to the level programmed by TXFIFOTHRES before running out of time
to send the packet before the next Start-Of-Frame .
This health counter measures the number of times this occurs to provide
feedback to selecting a proper TXSCHOH. Writing to this register will clear the
counter. The maximum value is 31.
Reserved
Scheduler overhead
This register adds an additional fixed offset to the schedule time estimator
described above as T
should limit the number of back-off events captured in the TXSCHHEALTH to
less than 10 per second in a highly utilized bus. Choosing a value that is too
high for this register is not desired as it can needlessly reduce USB utilization.
The time unit represented in this register is 1.267  s when a device is
connected in High-Speed Mode.
The time unit represented in this register is 6.333  s when a device is
connected in Low/Full Speed Mode.
Reserved
All information provided in this document is subject to legal disclaimers.
s
p
then the packet attempt ceases and the packet is tried at a later time.
ff
remains before the end of the (micro) frame. If so it proceeds to
. As an approximation, the value chosen for this register
Rev. 00.13 — 20 July 2011
ff
) described below.
Chapter 21: LPC18xx USB1 Host/Device controller
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0x2
0x0
-
0x0
457 of 1164
Access
R/W
R/W
-
R/W