LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 647

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
26.7.5.1 Match register in Edge-Aligned mode
26.7.5.2 Match register in Center-Aligned mode
26.7.5.3 0 and 100% duty cycle
26.7.5 MCPWM Match 0-2 registers
26.7.6 MCPWM Dead-time register
These registers also have “write” and “operating” versions as described above for the
Limit registers, and the operating registers are also compared to the channels’ TCs. See
26.7.4
The Match and Limit registers control the MCO0-2 outputs. If a Match register is to have
any effect on its channel’s operation, it must contain a smaller value than the
corresponding Limit register.
Table 557. MCPWM Match 0 to 2 registers (MAT - addresses 0x400A 0030 (MAT0),
If the channel’s CENTER bit in CON is 0 selecting edge-aligned mode, a match between
TC and MAT switches the channel’s B output from “active” to “passive” state. If the
channel’s CENTER and DTE bits in CON are both 0, the match simultaneously switches
the channel’s A output from “passive” to “active” state.
If the channel’s CENTER bit is 0 but the DTE bit is 1, the match triggers the channel’s
deadtime counter to begin counting -- when the deadtime counter expires, the channel’s A
output switches from “passive” to “active” state.
If the channel’s CENTER bit in CON is 1 selecting center-aligned mode, a match between
TC and MAT while the TC is incrementing switches the channel’s B output from “active” to
“passive” state, and a match while the TC is decrementing switches the A output from
“active” to “passive”. If the channel’s CENTER bit in CON is 1 but the DTE bit is 0, a match
simultaneously switches the channel’s other output in the opposite direction.
If the channel’s CENTER and DTE bits are both 1, a match between TC and MAT triggers
the channel’s deadtime counter to begin counting -- when the deadtime counter expires,
the channel’s B output switches from “passive” to “active” if the TC was counting up at the
time of the match, and the channel’s A output switches from “passive” to “active” if the TC
was counting down at the time of the match.
To lock a channel’s MCO outputs at the state “B active, A passive”, write its Match register
with a higher value than you write to its Limit register. The match never occurs.
To lock a channel’s MCO outputs at the opposite state, “A active, B passive”, simply write
0 to its Match register.
This register holds the dead-time values for the three channels. If a channel’s DTE bit in
CON is 1 to enable its dead-time counter, the counter counts down from this value
whenever one its channel’s outputs changes from “active” to “passive” state. When the
dead-time counter reaches 0, the channel changes its other output from “passive” to
“active” state.
Bit
31:0
above for details of reading and writing both Limit and Match registers.
Symbol
MCMAT
0x400A 0034 (MAT1), 0x400A 0038 (MAT2)) bit description
All information provided in this document is subject to legal disclaimers.
Description
Match value.
Rev. 00.13 — 20 July 2011
Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM)
Reset value
0xFFFF FFFF
UM10430
© NXP B.V. 2011. All rights reserved.
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