LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 403

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
20.8.1.7 Asynchronous Transaction scheduling and buffer management
20.8.1.8 Periodic Transaction scheduling and buffer management
Table 340. Split state machine properties
The following USB 2.0 specification items are implemented in the embedded Transaction
Translator:
The following USB 2.0 specification items are implemented in the embedded Transaction
Translator:
Start-split
Complete-split
1. USB 2.0 specification, section 11.17.3: Sequencing is provided & a packet length
2. USB 2.0 specification, section 11.17.4: Transaction tracking for 2 data pipes.
3. USB 2.0 specification, section 11.17.5: Clear_TT_Buffer capability provided though
1. USB 2.0 specs, section 11.18.6.[1-2]:
2. USB 2.0 specs, section 11.18.6.[7-8]:
estimator ensures no full-speed/low-speed packet babbles into SOF time.
the use of the TTCTRL register.
– Abort of pending start-splits:
– Abort of pending complete-splits:
– Transaction tracking for up to 16 data pipes:
EOF (and not started in micro-frames 6)
Idle for more than 4 micro-frames
EOF
Idle for more than 4 micro-frames
Some applications may not require transaction tracking up to a maximum of 16
periodic data pipes. The option to limit the tracking to only 4 periodic data pipes
exists in the by changing the configuration constant
VUSB_HS_TT_PERIODIC_CONTEXTS to 4. The result is a significant gate count
savings to the core given the limitations implied.
Remark: Limiting the number of tracking pipes in the EMBedded TT to four (4) will
impose the restriction that no more than 4 periodic transactions
(INTERRUPT/ISOCHRONOUS) can be scheduled through the embedded TT per
frame. The number 16 was chosen in the USB specification because it is sufficient
to ensure that the high-speed to full- speed periodic pipeline can remain full.
All information provided in this document is subject to legal disclaimers.
Condition
All asynchronous buffers full.
All periodic buffers full.
Success for start of Async. Transaction.
Start Periodic Transaction.
Failed to find transaction in queue.
Transaction in Queue is Busy.
Transaction in Queue is Complete.
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
Emulate TT response
NAK
ERR
ACK
No Handshake (Ok)
Bus Time Out
NYET
[Actual Handshake from
LS/FS device]
UM10430
© NXP B.V. 2011. All rights reserved.
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