LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 604

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
24.6.14 SCT DMA request 0 and 1 registers
Table 512. SCT conflict resolution register (RES - address 0x4000 0058) bit description
The SCT includes two DMA request outputs. These registers enable the DMA requests to
be triggered when a particular event occurs or when a counter’s Match registers are
loaded from its Reload registers.
Bit
21:
20
23:
22
25:
24
27:
26
29:
28
31:
30
Symbol
O10RES
O11RES
O10RES
O13RES
O14RES
O15RES
All information provided in this document is subject to legal disclaimers.
Value Description
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
Rev. 00.13 — 20 July 2011
Effect of simultaneous set and clear on output 10.
No change.
Set output (or clear based on the SETCLR10 field).
Clear output (or set based on the SETCLR10 field).
Toggle output.
Effect of simultaneous set and clear on output 11.
No change.
Set output (or clear based on the SETCLR11 field).
Clear output (or set based on the SETCLR11 field).
Toggle output.
Effect of simultaneous set and clear on output 12.
No change.
Set output (or clear based on the SETCLR12 field).
Clear output (or set based on the SETCLR12 field).
Toggle output.
Effect of simultaneous set and clear on output 13.
No change.
Set output (or clear based on the SETCLR13 field).
Clear output (or set based on the SETCLR13 field).
Toggle output.
Effect of simultaneous set and clear on output 14.
No change.
Set output (or clear based on the SETCLR14 field).
Clear output (or set based on the SETCLR14 field).
Toggle output.
Effect of simultaneous set and clear on output 15.
No change.
Set output (or clear based on the SETCLR15 field).
Clear output (or set based on the SETCLR15 field).
Toggle output.
Chapter 24: LPC18xx State Configurable Timer (SCT)
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0
0
0
0
0
0