LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 982

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
42.4.5 Pin description
42.4.6 Register description
Table 929. CGU pin description
The register addresses of the CGU are shown in
Remark: The CGU is configured by the boot loader at reset and when waking up from
Deep power-down to produce a 72 MHz clock using PLL1. Note that this configuration is
not reflected in the reset values given in
Table 930. Register overview: CGU (base address 0x4005 0000)
Pin name/
function name
XTAL1
XTAL2
RTCX1
RTCX2
GP_CLKIN
ENET_TX_CLK
ENET_RX_CLK
CLKOUT
Name
-
-
-
-
-
FREQ_MON
XTAL_OSC_CTRL
PLL0_STAT
PLL0_CTRL
PLL0_MDIV
PLL0_NP_DIV
PLL1_STAT
PLL1_CTRL
IDIVA_CTRL
IDIVB_CTRL
IDIVC_CTRL
IDIVD_CTRL
IDIVE_CTRL
OUTCLK_0_CTRL
OUTCLK_1_CTRL
All information provided in this document is subject to legal disclaimers.
Direction
I
O
I
O
I
I
I
O
Access Address
R
R
R
R
-
R/W
R/W
R
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 00.13 — 20 July 2011
Crystal oscillator input
RTC 32 kHz oscillator input
RTC 32 kHz oscillator output
General purpose input clock
Description
Crystal oscillator output
Ethernet PHY transmit clock
Ethernet PHY receive clock
Clock output pin
0x014
0x01C
0x020
0x024
0x02C
0x030
offset
0x000
0x004
0x008
0x00C
0x010
0x018
0x028
0x034
0x038
0x03C
0x040
0x044
0x048
0x04C
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Frequency monitor register
Crystal oscillator control register
PLL0 status register
PLL0 control register
PLL0 M-divider register
PLL0 N/P-divider register
PLL1 status register
PLL1 control register
Integer divider A control register
Integer divider B control register
Integer divider C control register
Integer divider D control register
Integer divider E control register
Output stage 0 control register for
base clock BASE_SAFE_CLK
Output stage 1 control register for
base clock BASE_USB0_CLK
Table
930.
Table
930.
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
Reset value
0x0110 0106
0x0000 0500
0x1A00 0000
0x0000 0000
-
0x0000 0000
0x0000 0005
0x0000 0000
0x0100 0003
0x05F8 5B6A
0x000B 1002
0x0000 0001
0x0100 0003
0x0100 0000
0x0100 0000
0x0100 0000
0x0100 0000
0x0100 0000
0x0100 0800
0x0700 0000
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