LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 400

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
20.8 Deviations from EHCI standard
<Document ID>
User manual
20.8.1.1 Capability registers
20.8.1 Embedded Transaction Translator function
since this action is performed by hardware. During the transition, the software may see an
interrupt from the disconnect and/or other spurious interrupts (i.e. SOF/etc.) that may or
may not cascade and my be cleared by the soft reset depending on the software response
time.
After the core has entered device mode with help of the hardware assist, the DCD must
ensure that the ENDPTLISTADDR is programmed properly before the host sends a setup
packet. Since the end of the reset duration, which may be initiated quickly (a few
microseconds) after connect, will require at a minimum 50 ms, this is the time for which
the DCD must be ready to accept setup packets after having received notification that the
reset has been detected or simply that the OTG is in device mode which ever occurs first.
If the A-peripheral fails to see a reset after the controller enters device mode and engages
the D+-pull-up, the device controller interrupts the DCD signifying that a suspend has
occurred. This assist will ensure the parameter TA_BDIS_ACON_MAX = 3ms is met.
For the purposes of a dual-role Host/Device controller with support for On-The-Go
applications, it is necessary to deviate from the EHCI specification. Device operation and
On-The-Go operation is not specified in the EHCI and thus the implementation supported
in this core is specific to the LPC18xx. The host mode operation of the core is near EHCI
compatible with few minor differences documented in this section.
The particulars of the deviations occur in the areas summarized here:
The USB-HS OTG controller supports directly connected full and low speed devices
without requiring a companion controller by including the capabilities of a USB 2.0 high
speed hub transaction translator. Although there is no separate Transaction Translator
block in the system, the transaction translator function normally associated with a high
speed hub has been implemented within the DMA and Protocol engine blocks. The
embedded transaction translator function is an extension to EHCI interface but
makes use of the standard data structures and operational models that exist in the EHCI
specification to support full and low speed devices.
The following items have been added to the capability registers to support the embedded
Transaction Translator Function:
•
•
•
•
•
Embedded Transaction Translator – Allows direct attachment of FS and LS devices in
host mode without the need for a companion controller.
Device operation - In host mode the device operational registers are generally
disabled and thus device mode is mostly transparent when in host mode. However,
there are a couple exceptions documented in the following sections.
On-The-Go Operation - This design includes an On-The-Go controller.
N_TT bits added to HCSPARAMS – Host Control Structural Parameters (see
Table
N_PTT added to HCSPARAMS – Host Control Structural Parameters (see
302).
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
UM10430
© NXP B.V. 2011. All rights reserved.
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302).