LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1014

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
42.5.5.4 CCU1/2 branch clock status registers
Table 959. CCU1 branch clock configuration register (CLK_XXX_CFG, addresses 0x4005
Table 960. CCU2 branch clock configuration register (CLK_XXX_CFG, addresses 0x4005
Like the Configuration Register, each generated output clock from the CCU has a status
register. When the configuration register of an output clock is written into, the value of the
actual hardware signals may not be updated immediately because of the Auto or Wake-up
mechanism. The Status Register shows the current value of these signals. All output clock
Status Registers follow the format as described in
Bit
0
1
2
31:3
Bit
0
1
2
31:3
Symbol
RUN
AUTO
WAKEUP
-
Symbol
RUN
AUTO
WAKEUP
-
1100, 0x4005 1104,..., 0x4005 1A00) bit description
2100, 0x4005 2200,..., 0x4005 2800) bit description
All information provided in this document is subject to legal disclaimers.
Value
0
1
0
1
0
1
Value
0
1
0
1
0
1
Rev. 00.13 — 20 July 2011
Description
Run enable
Clock is disabled.
Clock is enabled.
Auto (AHB disable mechanism) enable
Auto is disabled.
Auto is enabled.
Wake-up mechanism enable
Wake-up is disabled.
Wake-up is enabled.
Reserved
Description
Run enable
Clock is disabled.
Clock is enabled.
Auto (AHB disable mechanism) enable
Auto is disabled.
Auto is enabled.
Wake-up mechanism enable
Wake-up is disabled.
Wake-up is enabled.
Reserved
Table 961
and
Table
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
962.
Reset
value
1
0
0
-
Reset
value
1
0
0
-
1014 of 1164
Access
R/W
R/W
R/W
-
Access
R/W
R/W
R/W
-