LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 491

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 412. MAC Debug register (MAC_DEBUG, address 0x4001 0024) bit description
<Document ID>
User manual
Bit
6:5
7
9:8
15:10
16
18:17
19
21:20
22
23
24
25
31:26
Symbol
RXFIFO
STAT
-
RXFIFOL
VL
-
TXIDLES
TAT
TXSTAT
PAUSE
TXFIFOS
TAT
TXFIFOS
TAT1
-
TXFIFOL
VL
TXFIFOF
ULL
22.6.10 MAC Remote wake-up frame filter register
Description
State of the RxFIFO read Controller:
00 = idle state
01 = reading frame data
10 = reading frame status (or time stamp)
11 = flushing the frame data and status
Reserved
Status of the RxFIFO Fill-level
00 = RxFIFO Empty
01 = RxFIFO fill-level below flow-control de-activate threshold
10 = RxFIFO fill-level above flow-control activate threshold
11 = RxFIFO Full
Reserved
When high, it indicates that the MAC MII transmit protocol engine is actively
transmitting data and not in IDLE state.
State of the MAC Transmit Frame Controller module:
00 = idle
01 = Waiting for Status of previous frame or IFG/backoff period to be over
10 = Generating and transmitting a PAUSE control frame (in full duplex mode)
11 = Transferring input frame for transmission
When high, it indicates that the MAC transmitter is in PAUSE condition (in full-duplex
only) and hence will not schedule any frame for transmission.
State of the TxFIFO read Controller
00 = idle state
01 = READ state (transferring data to MAC transmitter)
10 = Waiting for TxStatus from MAC transmitter
11 = Writing the received TxStatus or flushing the TxFIFO
When high, it indicates that the MTL TxFIFO Write Controller is active and
transferring data to the TxFIFO.
Reserved
When high, it indicates that the MTL TxFIFO is not empty and has some data left for
transmission.
When high, it indicates that the MTL TxStatus FIFO is full and hence the MTL will not
be accepting any more frames for transmission.
This is the address through which the remote Wake-up Frame Filter registers
(WKUPFMFILTER) are written/read by the Application. WKUPFMFILTER is actually a
pointer to eight (not transparent) such WKUPFMFILTER registers. Eight sequential Writes
to this address (0x028) will write all WKUPFMFILTER registers. Eight sequential Reads
from this address (0x028) will read all WKUPFMFILTER registers. See
for details.
Remark: Do not use bit-banding for this register.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 22: LPC18xx Ethernet
…continued
UM10430
Section 22.7.1.1
© NXP B.V. 2011. All rights reserved.
Reset
value
-
491 of 1164
Access
RO