LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 747

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 690: UART1 Receiver Buffer Register when DLAB = 0 (RBR - address 0x4008 2000 ) bit description
Table 691: UART1 Transmitter Holding Register when DLAB = 0 (THR - address 0x4008 2000 ) bit description
<Document ID>
User manual
Bit
7:0
31:8
Bit
7:0
31:8
Symbol Description
RBR
-
Symbol Description
THR
-
33.5.1 UART1 Receiver Buffer Register (when DLAB = 0)
33.5.2 UART1 Transmitter Holding Register (when DLAB = 0)
33.5.3 UART1 Divisor Latch LSB and MSB Registers (when DLAB = 1)
Receiver Buffer.
Contains the oldest received byte in the UART1 RX FIFO.
Reserved, the value read from a reserved bit is not defined.
Transmit Holding Register.
Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1
transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the
transmitter is available.
Reserved, user software should not write ones to reserved bits.
The U1RBR is the top byte of the UART1 RX FIFO. The top byte of the RX FIFO contains
the oldest character received and can be read via the bus interface. The LSB (bit 0)
represents the “oldest” received data bit. If the character received is less than 8 bits, the
unused MSBs are padded with zeroes.
The Divisor Latch Access Bit (DLAB) in U1LCR must be zero in order to access the
U1RBR. The U1RBR is always read-only.
Since PE, FE and BI bits correspond to the byte sitting on the top of the RBR FIFO (i.e.
the one that will be read in the next read from the RBR), the right approach for fetching the
valid pair of received byte and its status bits is first to read the content of the U1LSR
register, and then to read a byte from the U1RBR.
The write-only U1THR is the top byte of the UART1 TX FIFO. The top byte is the newest
character in the TX FIFO and can be written via the bus interface. The LSB represents the
first bit to transmit.
The Divisor Latch Access Bit (DLAB) in U1LCR must be zero in order to access the
U1THR. The U1THR is write-only.
The UART1 Divisor Latch is part of the UART1 Baud Rate Generator and holds the value
used, along with the Fractional Divider, to divide the APB clock (PCLK) in order to produce
the baud rate clock, which must be 16x the desired baud rate. The U1DLL and U1DLM
registers together form a 16-bit divisor where U1DLL contains the lower 8 bits of the
divisor and U1DLM contains the higher 8 bits of the divisor. A 0x0000 value is treated like
a 0x0001 value as division by zero is not allowed.The Divisor Latch Access Bit (DLAB) in
U1LCR must be one in order to access the UART1 Divisor Latches. Details on how to
select the right value for U1DLL and U1DLM can be found later in this chapter, see
Section
33.5.16.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 33: LPC18xx UART1
UM10430
© NXP B.V. 2011. All rights reserved.
Reset value
undefined
NA
Reset value
NA
NA
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