LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 744

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LPC1837FET256,551

Manufacturer Part Number
LPC1837FET256,551
Description
Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
Manufacturer
NXP Semiconductors
Series
LPC18xxr

Specifications of LPC1837FET256,551

Core
ARM Cortex M3
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
 Details
Other names
935293795551
NXP Semiconductors
33.4 Pin description
Table 688: UART1 Pin description
<Document ID>
User manual
Pin
RXD1 Input
TXD1 Output
CTS1 Input
DCD1 Input
DSR1 Input
DTR1 Output
RI1
RTS1 Output
Direction Description
Input
Serial Input. Serial receive data.
Serial Output. Serial transmit data.
Clear To Send. Active low signal indicates if the external modem is ready to accept transmitted data via
TXD1 from the UART1. In normal operation of the modem interface (U1MCR[4] = 0), the complement
value of this signal is stored in U1MSR[4]. State change information is stored in U1MSR[0] and is a
source for a priority level 4 interrupt, if enabled (U1IER[3] = 1).
Clear to send. CTS1 is an asynchronous, active low modem status signal. Its condition can be checked
by reading bit 4 (CTS) of the modem status register. Bit 0 (DCTS) of the Modem Status Register (MSR)
indicates that CTS1 has changed states since the last read from the MSR. If the modem status interrupt
is enabled when CTS1 changes levels and the auto-cts mode is not enabled, an interrupt is generated.
CTS1 is also used in the auto-cts mode to control the transmitter.
Data Carrier Detect. Active low signal indicates if the external modem has established a
communication link with the UART1 and data may be exchanged. In normal operation of the modem
interface (U1MCR[4]=0), the complement value of this signal is stored in U1MSR[7]. State change
information is stored in U1MSR3 and is a source for a priority level 4 interrupt, if enabled (U1IER[3] = 1).
Data Set Ready. Active low signal indicates if the external modem is ready to establish a
communications link with the UART1. In normal operation of the modem interface (U1MCR[4] = 0), the
complement value of this signal is stored in U1MSR[5]. State change information is stored in U1MSR[1]
and is a source for a priority level 4 interrupt, if enabled (U1IER[3] = 1).
Data Terminal Ready. Active low signal indicates that the UART1 is ready to establish connection with
external modem. The complement value of this signal is stored in U1MCR[0].
The DTR pin can also be used as an RS-485/EIA-485 output enable signal.
Ring Indicator. Active low signal indicates that a telephone ringing signal has been detected by the
modem. In normal operation of the modem interface (U1MCR[4] = 0), the complement value of this
signal is stored in U1MSR[6]. State change information is stored in U1MSR[2] and is a source for a
priority level 4 interrupt, if enabled (U1IER[3] = 1).
Request To Send. Active low signal indicates that the UART1 would like to transmit data to the external
modem. The complement value of this signal is stored in U1MCR[1].
In auto-rts mode, RTS1 is used to control the transmitter FIFO threshold logic.
Request to send. RTS1 is an active low signal informing the modem or data set that the UART is ready
to receive data. RTS1 is set to the active (low) level by setting the RTS modem control register bit and is
set to the inactive (high) level either as a result of a system reset or during loop-back mode operations or
by clearing bit 1 (RTS) of the MCR. In the auto-rts mode, RTS1 is controlled by the transmitter FIFO
threshold logic.
The RTS pin can also be used as an RS-485/EIA-485 output enable signal.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 33: LPC18xx UART1
UM10430
© NXP B.V. 2011. All rights reserved.
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