LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 736

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
32.6 Functional description
<Document ID>
User manual
32.5.19 UART Transmit Enable Register
32.6.1 Asynchronous mode
32.6.2 Synchronous mode
In addition to being equipped with full hardware flow control (auto-cts and auto-rts
mechanisms described above), TER enables implementation of software flow control.
When TxEn = 1, UART transmitter will keep sending data as long as they are available. As
soon as TxEn becomes 0, UART transmission will stop.
Table 686
Table 686. UART Transmit Enable Register (TER - addresses 0x4008 1030 (UART0), 0x400C
<tbd>
When the synchronous receiver/ transmitter feature is configured (USART), the serial
interface is extended with a serial input and output clock and an output enable for
controlling the clock pad.
By default transmission and reception in synchronous mode operates uses the same
protocol as in asynchronous mode. Synchronous mode can be configured using the
Synchronous Mode Control Register. This register allows to control:
Data is shifted in the receive shift register at the sampling edge of the serial clock.
Bit
0
31:1 -
Fig 90. USART serial interface protocol
•
•
•
•
•
The direction of the serial clock, i.e. synchronous slave or master mode
The sampling edge of the serial clock
Two-stage or one stage synchronization of the input serial clock during transmission
During synchronous master mode, the clock can be continuous or disabled when in
idle or break mode
The transmission of start and stop bits can be omitted. Valid data is identified by a
running clock. Sampling is always done on the falling edge of the serial clock
Symbol
TXEN
describes how to use TXEn bit in order to achieve software flow control.
1030 (UART2), 0x400C 205C (UART3)) bit description
All information provided in this document is subject to legal disclaimers.
Description
Transmit enable.
After reset transmission is enabled. When the txen bit is
de-asserted, no data will be transmitted although data may be
pending in the TSR or THR.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Rev. 00.13 — 20 July 2011
Chapter 32: LPC18xx USART0_2_3
UM10430
© NXP B.V. 2011. All rights reserved.
Reset value
1
-
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