LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 300

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 225. Control Register (CTRL, address 0x4000 4000) bit description
<Document ID>
User manual
Bit
6
7
8
9
10
Symbol
READ_WAIT
SEND_IRQ_RESPONS
E
ABORT_READ_DATA
SEND_CCSD
SEND_AUTO_STOP_C
CSD
Value
0
1
0
1
0
1
0
1
0
1
All information provided in this document is subject to legal disclaimers.
Description
read_wait. For sending read-wait to SDIO cards.
Clear read wait
Assert read wait
Send irq response. Bit automatically clears once response is sent. To
wait for MMC card interrupts, host issues CMD40, and
DWC_mobile_storage waits for interrupt response from MMC card(s).
In meantime, if host wants DWC_mobile_storage to exit waiting for
interrupt state, it can set this bit, at which time DWC_mobile_storage
command state-machine sends CMD40 response on bus and returns
to idle state.
No change
Send auto IRQ response
Abort read data. Used in SDIO card suspend sequence.
No change
After suspend command is issued during read-transfer, software polls
card to find when suspend happened. Once suspend occurs,
software sets bit to reset data state-machine, which is waiting for next
block of data. Bit automatically clears once data state machine resets
to idle.
Send ccsd. When set, DWC_mobile_storage sends CCSD to CE-ATA
device. Software sets this bit only if current command is expecting
CCS (that is, RW_BLK) and interrupts are enabled in CE-ATA device.
Once the CCSD pattern is sent to device, DWC_mobile_storage
automatically clears send_ccsd bit. It also sets Command Done (CD)
bit in RINTSTS register and generates interrupt to host if Command
Done interrupt is not masked.
NOTE: Once send_ccsd bit is set, it takes two card clock cycles to
drive the CCSD on the CMD line. Due to this, during the boundary
conditions it may happen that CCSD is sent to the CE-ATA device,
even if the device signalled CCS.
Clear bit if DWC_mobile_storage does not reset the bit.
Send Command Completion Signal Disable (CCSD) to CE-ATA
device
Send auto stop ccsd. NOTE: Always set send_auto_stop_ccsd and
send_ccsd bits together; send_auto_stop_ccsd should not be set
independent of send_ccsd. When set, DWC_Mobile_Storage
automatically sends internallygenerated STOP command (CMD12) to
CE-ATA device. After sending internally-generated STOP command,
Auto Command Done (ACD) bit in RINTSTS is set and generates
interrupt to host if Auto Command Done interrupt is not masked. After
sending the CCSD, DWC_mobile_storage automatically clears
send_auto_stop_ccsd bit.
Clear bit if DWC_mobile_storage does not reset the bit.
Send internally generated STOP after sending CCSD to CE-ATA
device.
Rev. 00.13 — 20 July 2011
Chapter 18: LPC18xx SD/MMC interface
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0
0
0
0
0