LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 836

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
36.6.3.6 CAN interrupt pending 2 register
36.6.3.7 CAN message valid 1 register
36.6.3.8 CAN message valid 2 register
Table 790. CAN interrupt pending 1 register (IR1, address 0x400E 2140 (C_CAN0) and
This register contains the INTPND bits of message objects 32 to 17. By reading out the
INTPND bits, the CPU can check for which Message Object an interrupt is pending. The
INTPND bit of a specific Message Object can be set/reset by the CPU via the IFx
Message Interface Registers or by the Message Handler after reception or after a
successful transmission of a frame. This will also affect the value of INTPND in the
Interrupt Register.
Table 791. CAN interrupt pending 2 register (IR2, addresses 0x400E 2144 (C_CAN0) and
This register contains the MSGVAL bits of message objects 16 to 1. By reading out the
MSGVAL bits, the CPU can check which Message Object is valid. The MSGVAL bit of a
specific Message Object can be set/reset by the CPU via the IFx Message Interface
Registers.
Table 792. CAN message valid 1 register (MSGV1, addresses 0x400E 2160 (C_CAN0) and
This register contains the MSGVAL bits of message objects 32 to 17. By reading out the
MSGVAL bits, the CPU can check which Message Object is valid. The MSGVAL bit of a
specific Message Object can be set/reset by the CPU via the IFx Message Interface
Registers.
Bit
15:0
31:16 -
Bit
15:0
31:16 -
Bit
15:0
31:16 -
Symbol
INTPND16_1
Symbol
INTPND32_17 Interrupt pending bits of message objects 32 to 17.
Symbol
MSGVAL16_1
0x400A 4140 (C_CAN1)) bit description
0x400A 4144 (C_CAN1)) bit description
0x400A 4160 (C_CAN1)) bit description
All information provided in this document is subject to legal disclaimers.
Description
Interrupt pending bits of message objects 16 to 1.
0 = This message object is ignored by the message
handler.
1 = This message object is the source of an interrupt.
Reserved
Description
0 = This message object is ignored by the message
handler.
1 = This message object is the source of an interrupt.
Reserved
Rev. 00.13 — 20 July 2011
Description
Message valid bits of message objects 16 to 1.
0 = This message object is ignored by the message
handler.
1 = This message object is configured and should be
considered by the message handler.
Reserved
Chapter 36: LPC18xx C_CAN
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0x00
-
Reset
value
0x00
-
Reset
value
0x00
-
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Access
R
-
Access
R
-
Access
R
-