LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 507

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 429. DMA Interrupt enable register (DMA_INT_EN, address 0x4001 101C) bit description
<Document ID>
User manual
Bit
15
16
31:17
Symbol
AIE
NIE
-
Description
Abnormal interrupt summary enable
When this bit is set, an Abnormal Interrupt is enabled. When this bit is reset, an
Abnormal Interrupt is disabled. This bit enables the following bits
DMA_STAT register, bit 1: Transmit process stopped
DMA_STAT register, bit 3: Transmit jabber timeout
DMA_STAT register, bit 4: Receive overflow
DMA_STAT register, bit 5: Transmit underflow
DMA_STAT register, bit 7: Receiver buffer unavailable
DMA_STAT register, bit 8: Receive process stopped
DMA_STAT register, bit 9: Receive watchdog timeout
DMA_STAT register, bit 10: Early transmit interrupt
DMA_STAT register, bit 13: Fatal bus error
Normal interrupt summary enable
When this bit is set, a normal interrupt is enabled. When this bit is reset, a normal
interrupt is disabled. This bit enables the following bits:
DMA_STAT register, bit 0: Transmit interrupt
DMA_STAT register, bit 2: Transmit buffer unavailable
DMA_STAT register, bit 6: Receive interrupt
DMA_STAT register, bit 14: Early receive interrupt
Reserved
The interrupt (sbd_intr_o_interrupt) is generated as shown in
when the NIS/AIS Status bit is asserted and the corresponding Interrupt Enable bits
(NIE/AIE) are enabled.
Fig 44. Interrupt generation
ERE
TPS
TSE
FBE
ERI
TIE
FBI
TI
All information provided in this document is subject to legal disclaimers.
AND
AND
AND
AND
Rev. 00.13 — 20 July 2011
OR
OR
NIE
AIE
NIS
AIS
AN D
AN D
Chapter 22: LPC18xx Ethernet
Figure
OR
44. It is asserted
…continued
UM10430
© NXP B.V. 2011. All rights reserved.
sbd _intr_o
Reset
value
0
0
0
507 of 1164
Access
R/W
R/W
RO