LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 910

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

40.1 How to read this chapter
40.2 Introduction
40.3 Features
40.4 Description
<Document ID>
User manual
The flash programming interface is available for parts with on-chip flash. A reduced set of
ISP commands is supported for flashless parts (see
of the boot process for flashless parts.
The boot loader controls initial operation after reset and also provides the tools for
programming the flash memory. This could be initial programming of a blank device,
erasure and re-programming of a previously programmed device, or programming of the
flash memory by the application program in a running system.
The flash boot loader code is executed every time the part is powered on or reset. The
loader can execute the ISP command handler or the user application code. A LOW level
after reset at pin P2_7 is considered an external hardware request to start the ISP
command handler. Assuming that power supply pins are on their nominal levels when the
rising edge on RESET pin is generated, it may take up to 3 ms before P2_7 is sampled
and the decision on whether to continue with user code or ISP handler is made. If P2_7 is
sampled low and the watchdog overflow flag is set, the external hardware request to start
the ISP command handler is ignored. If there is no request for the ISP command handler
execution (P2_7 is sampled HIGH after reset), a search is made for a valid user program.
If a valid user program is found then the execution control is transferred to it. If a valid user
program is not found, the auto-baud routine is invoked.
Pin P2_7 is used as a hardware request signal for ISP and therefore requires special
attention. Since P2_7 is in high impedance mode after reset, it is important that the user
provides external hardware (a pull-up resistor or other device) to put the pin in a defined
state. Otherwise unintended entry into ISP mode may occur.
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UM10430
Chapter 40: LPC18xx flash programming interface
Rev. 00.13 — 20 July 2011
In-System Programming: In-System programming (ISP) is programming or
reprogramming the on-chip flash memory, using the boot loader software and UART0
serial port. This can be done when the part resides in the end-user board.
For parts without on-chip flash, ISP allows to load data to on-chip SRAM and to
execute code from on-chip SRAM.
In Application Programming: In-Application (IAP) programming is performing erase
and write operation on the on-chip flash memory, as directed by the end-user
application code.
Flash signature generation: built-in hardware can generate a signature for a range of
flash addresses or for the entire flash memory.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Table
843). See
Chapter 3
© NXP B.V. 2011. All rights reserved.
User manual
for details
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