LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 482

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 403. MAC Configuration register (MAC_CONFIG, address 0x4001 0000) bit description
<Document ID>
User manual
Bit
6:5
7
8
9
10
11
Symbol
BL
ACS
-
DR
IPC
DM
Description
Back-Off Limit
The Back-Off limit determines the random integer number (r) of slot time delays
(4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) the MAC waits
before rescheduling a transmission attempt during retries after a collision. This bit is
applicable only to Half-Duplex mode and is reserved (RO) in Full-Duplex-only
configuration.
where n = retransmission attempt. The random integer r takes the value in the range
0  r  2
Automatic Pad/CRC Stripping
When this bit is set, the MAC strips the Pad/FCS field on incoming frames only if the
length’s field value is less than or equal to 1,500 bytes. All received frames with
length field greater than or equal to 1,501 bytes are passed to the application without
stripping the Pad/FCS field.
When this bit is reset, the MAC will pass all incoming frames to the Host unmodified.
Link Up/Down
Indicates whether the link is up or down during the transmission of configuration in
SMII interface:
0 = Link down
1 = Link up
Disable Retry
When this bit is set, the MAC will attempt only 1 transmission. When a collision occurs
on the MII, the MAC will ignore the current frame transmission and report a Frame
Abort with excessive collision error in the transmit frame status.
When this bit is reset, the MAC will attempt retries based on the settings of BL. This
bit is applicable only to Half-Duplex mode and is reserved (RO with default value) in
Full- Duplex-only configuration.
Checksum Offload
When this bit is set, the MAC calculates the 16-bit one’s complement of the one’s
complement sum of all received Ethernet frame payloads. It also checks whether the
IPv4 Header checksum (assumed to be bytes 25–26 or 29–30 (VLAN-tagged) of the
received Ethernet frame) is correct for the received frame and gives the status in the
receive status word. The MAC core also appends the 16-bit checksum calculated for
the IP header datagram payload (bytes after the IPv4 header) and appends it to the
Ethernet frame transferred to the application (when Type 2 COE is deselected). When
this bit is reset, this function is disabled.
When Type 2 COE is selected, this bit, when set, enables IPv4 checksum checking
for received frame payload’s TCP/UDP/ICMP headers. When this bit is reset, the
COE function in the receiver is disabled and the corresponding PCE and IP HCE
status bits (see <tbd>) are always cleared.
Duplex Mode
When this bit is set, the MAC operates in a Full-Duplex mode where it can transmit
and receive simultaneously.
•
•
•
•
00: k = min (n, 10)
01: k = min (n, 8)
10: k = min (n, 4)
11: k = min (n, 1)
k
.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 22: LPC18xx Ethernet
…continued
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
0
0
0
0
0
482 of 1164
Access
R/W
R/W
R/W
R/W
R/W
R/W