LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 461

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 387. USB Endpoint NAK Enable register in device mode (ENDPTNAKEN - address 0x4000 717C) bit
Table 388. Port Status and Control register in device mode (PORTSC1_D - address 0x4000 7184) bit description
<Document ID>
User manual
Bit
3:0
15:4
19:16 EPTNE
31:20 -
Bit
0
1
2
Symbol
CCS
CSC
PE
Symbol
EPRNE
-
21.6.14.2 Host mode
21.6.15.1 Device mode
description
21.6.15 Port Status and Control register (PORTSC1)
Value Description
0
1
-
1
This register is not used in host mode.
The device controller implements one port register, and it does not support power control.
Port control in device mode is used for status port reset, suspend, and current connect
status. It is also used to initiate test mode or force signaling. This register allows software
to put the PHY into low-power Suspend mode and disable the PHY clock.
Description
Rx endpoint NAK enable
Each bit enables the corresponding RX NAK bit. If this bit is set and the
corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set.
Bit 3 corresponds to endpoint 3.
...
Bit 1 corresponds to endpoint 1.
Bit 0 corresponds to endpoint 0.
Reserved
Tx endpoint NAK
Each bit enables the corresponding TX NAK bit. If this bit is set and the
corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set.
Bit 3 corresponds to endpoint 3.
...
Bit 1 corresponds to endpoint 1.
Bit 0 corresponds to endpoint 0.
Reserved
Current connect status
Device not attached
A zero indicates that the device did not attach successfully or was forcibly
disconnected by the software writing a zero to the Run bit in the USBCMD
register. It does not state the device being disconnected or suspended.
Device attached.
A one indicates that the device successfully attached and is operating in
either high-speed mode or full-speed mode as indicated by the High Speed
Port bit in this register.
Not used in device mode
Port enable.
This bit is always 1. The device port is always enabled.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 21: LPC18xx USB1 Host/Device controller
UM10430
Reset
value
0
0
1
© NXP B.V. 2011. All rights reserved.
Reset
value
0x00
-
0x00
-
461 of 1164
RO
-
Access
R/W
-
R/W
-
Access
RO