LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 260

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
15.6 Functional description
<Document ID>
User manual
15.5.3.8 GPIO port clear registers
15.5.3.9 GPIO port toggle registers
15.6.1 Reading pin state
15.6.2 GPIO output
Each GPIO port has one output clear register. Output bits can be cleared by writing ones
to these write-only registers, regardless of MASK registers.
Table 191. GPIO port clear register (CLR, addresses 0x400F 6280 (CLR0) to 0x400F 629C
Each GPIO port has one output toggle register. Output bits can be
toggled/inverted/complemented by writing ones to these write-only registers, regardless of
MASK registers.
Table 192. GPIO port toggle register (NOT, addresses 0x400F 6300 (NOT0) to 0x400F 632C
Software can read the state of all GPIO pins except those selected for analog input or
output in the “I/O Configuration” logic. A pin does not have to be selected for GPIO in “I/O
Configuration” in order to read its state. There are four ways to read pin state:
Each GPIO pin has an output bit in the GPIO block. These output bits are the targets of
write operations “to the pins”. Two conditions must be met in order for a pin’s output bit to
be driven onto the pin:
Bit
31:0
Bit
31:0
1. The pin must be selected for GPIO operation in the “I/O Configuration” block, and
•
•
•
•
The state of a single pin can be read with 7 high-order zeros from a Byte Pin register.
The state of a single pin can be read in all bits of a byte, halfword, or word from a
Word Pin register.
The state of multiple pins in a port can be read as a byte, halfword, or word from a
PORT register.
The state of a selected subset of the pins in a port can be read from a Masked Port
(MPORT) register. Pins having a 1 in the port’s Mask register will read as 0 from its
MPORT register.
Symbol Description
NOTP0
Symbol
CLR
(CLR7)) bit description
(NOT7)) bit description
All information provided in this document is subject to legal disclaimers.
Toggle output bits (bit 0 = GPIOn[0], bit 1 = GPIOn[1], ..., bit
31 = GPIOn[31]):
0 = no operation.
1 = Toggle output bit.
Rev. 00.13 — 20 July 2011
Description
Clear output bits (bit 0 = GPIOn[0], bit 1 = GPIOn[1],
..., bit 31 = GPIOn[31]):
0 = No operation.
1 = Clear output bit.
Chapter 15: LPC18xx GPIO
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
NA
Reset
value
NA
260 of 1164
Access
WO
Access
WO