LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 512

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
22.7.1.3 Magic packet detection
22.7.1.4 System considerations during power-down
The Magic Packet frame is based on a method that uses Advanced Micro Device’s Magic
Packet technology to power up the sleeping device on the network. The MAC receives a
specific packet of information, called a Magic Packet, addressed to the node on the
network.
Only Magic Packets that are addressed to the device or a broadcast address will be
checked to determine whether they meet the wake-up requirements. Magic Packets that
pass the address filtering (unicast or broadcast) will be checked to determine whether
they meet the remote Wake-on-LAN data format of 6 bytes of all ones followed by a MAC
Address appearing 16 times.
The application enables Magic Packet wake-up by writing a 1 to Bit 1 of the PMT Control
and Status register. The PMT block constantly monitors each frame addressed to the
node for a specific Magic Packet pattern. Each frame received is checked for a 0xFFFF
FFFF FFFF pattern following the destination and source address field. The PMT block
then checks the frame for 16 repetitions of the MAC address without any breaks or
interruptions. In case of a break in the 16 repetitions of the address, the 0xFFFF FFFF
FFFF pattern is scanned for again in the incoming frame. The 16 repetitions can be
anywhere in the frame, but must be preceded by the synchronization stream (0xFFFF
FFFF FFFF). The device will also accept a multicast frame, as long as the 16 duplications
of the MAC address are detected.
If the MAC address of a node is 0x0011 2233 4455, then the MAC scans for the data
sequence:
Magic Packet detection is updated in the PMT Control and Status register for Magic
Packet received. A PMT interrupt to the Application triggers a read to the PMT CSR to
determine whether a Magic Packet frame has been received.
MAC neither gates nor stops clocks when Power-down mode is enabled. Power saving by
clock gating must be done outside the core by the application. The receive data path must
be clocked with ENET_RX_CLK during Power-down mode because it is involved in magic
packet/wake-on-LAN frame detection. However, the transmit path and the application path
clocks can be gated off during Power-down mode.
The PMT interrupt is asserted when a valid wake-up frame is received. This signal is
generated in the receive clock domain
The recommended power-down and wake-up sequence is as follows.
1. Disable the Transmit DMA and wait for any previous frame transmissions to complete.
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
...CRC
These transmissions can be detected when Transmit Interrupt (see DMA_STAT
register bit NIS;
All information provided in this document is subject to legal disclaimers.
Table
Rev. 00.13 — 20 July 2011
427) is received.
Chapter 22: LPC18xx Ethernet
UM10430
© NXP B.V. 2011. All rights reserved.
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