LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 432

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
20.11 USB power optimization
<Document ID>
User manual
20.11.1 USB power states
Table 357. Error interrupt events
The USB-HS core is a fully synchronous static design. The power used by the design is
dependent on the implementation technology used to fabricate the design and on the
application usage of the core. Applications that transfer more data or use a greater
number of packets to be sent will consume a greater amount of power.
Because the design is synchronous and static, power may be conserved by reducing the
transitions of the clock net. This may be done in several ways.
A device may suspend operations autonomously by disconnecting from the USB, or, in
response to the suspend signaling, the USB has moved it into the suspend state. A host
can suspend operation autonomously, or it can command portions or the entire USB to
transition into the suspend state.
The USB provides a mechanism to place segments of the USB or the entire USB into a
low-power suspend state. USB bus powered devices are required to respond to a 3ms
lack of activity on the USB bus by going into a suspend state. In the USB-HS core
software is notified of the suspend condition via the transition in the PORTSC register.
Optionally an interrupt can be generated which is controlled by the port change Detect
Enable bit in the USBINTR control register. Software then has 7 ms to transition a bus
powered device into the suspend state. In the suspend state, a USB device has a
maximum USB bus power budget of 500A. In general, to achieve that level of power
conservation, most of the device circuits will need to be switched off, or clock at an
extremely low frequency. This can be accomplished by suspending the clock.
The implementation of low power states in the USB-HS core is dependant on the use of
the device role (host or peripheral), whether the device is bus powered, and the selected
clock architecture of the core.
Interrupt
USB error interrupt
System error
1. Reduce the clock frequency to the core. The clock frequency may not be reduced
2. Reduce transition on the clock net through the use of clock gating methods. (The
3. The clock may be shut off to the core entirely to conserve power. Again this may only
below the minimum recommended operating frequency of the core without first
disabling the USB operation.
LPC18xx is synthesized using this mechanism).
be done after the USB operations on the bus have been disabled.
All information provided in this document is subject to legal disclaimers.
Action
This error is redundant because it combines USB Interrupt and an error
status in the dTD. The DCD will more aptly handle packet-level errors by
checking dTD status field upon receipt of USB Interrupt (w/
ENDPTCOMPLETE).
Unrecoverable error. Immediate Reset of core; free transfers buffers in
progress and restart the DCD.
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
UM10430
© NXP B.V. 2011. All rights reserved.
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