LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1155

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
23.5.1
23.5.1.1
23.5.1.2
23.5.1.3
23.6
23.6.1
23.6.1.1
23.6.2
23.6.3
23.6.4
23.6.5
23.6.6
23.6.7
23.6.8
23.6.9
23.6.10
23.6.11
23.6.12
23.6.13
23.6.14
23.6.15
23.6.16
23.6.17
23.6.18
23.6.19
23.6.20
23.6.21
23.6.22
23.6.23
23.6.24
23.6.25
Chapter 24: LPC18xx State Configurable Timer (SCT)
24.1
24.2
24.3
24.4
24.5
24.6
24.6.1
24.6.2
24.6.3
24.6.4
24.6.5
24.6.6
24.6.7
24.6.8
24.6.9
24.6.10
24.6.11
24.6.12
24.6.13
24.6.14
24.6.15
24.6.16
24.6.17
<Document ID>
User manual
Register description . . . . . . . . . . . . . . . . . . . 545
How to read this chapter . . . . . . . . . . . . . . . . 587
Basic configuration . . . . . . . . . . . . . . . . . . . . 587
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587
General description . . . . . . . . . . . . . . . . . . . . 588
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 589
Register description . . . . . . . . . . . . . . . . . . . 589
Signal usage . . . . . . . . . . . . . . . . . . . . . . . . . 543
Signals used for single panel STN displays . 543
Signals used for dual panel STN displays . . 544
Signals used for TFT displays . . . . . . . . . . . 544
Horizontal Timing register . . . . . . . . . . . . . . 546
Horizontal timing restrictions. . . . . . . . . . . . . 547
Vertical Timing register . . . . . . . . . . . . . . . . 547
Clock and Signal Polarity register . . . . . . . . 548
Line End Control register . . . . . . . . . . . . . . . 550
Upper Panel Frame Base Address register . 551
Lower Panel Frame Base Address register . 551
LCD Control register . . . . . . . . . . . . . . . . . . 552
Interrupt Mask register . . . . . . . . . . . . . . . . . 554
Raw Interrupt Status register . . . . . . . . . . . . 554
Masked Interrupt Status register . . . . . . . . . 555
Interrupt Clear register . . . . . . . . . . . . . . . . . 555
Upper Panel Current Address register . . . . . 556
Lower Panel Current Address register . . . . . 556
Color Palette registers . . . . . . . . . . . . . . . . . 557
Cursor Image registers . . . . . . . . . . . . . . . . 557
Cursor Control register . . . . . . . . . . . . . . . . . 558
Cursor Configuration register . . . . . . . . . . . . 558
Cursor Palette register 0 . . . . . . . . . . . . . . . 559
Cursor Palette register 1 . . . . . . . . . . . . . . . 559
Cursor XY Position register . . . . . . . . . . . . . 560
Cursor Clip Position register . . . . . . . . . . . . 560
Cursor Interrupt Mask register . . . . . . . . . . . 561
Cursor Interrupt Clear register . . . . . . . . . . . 561
Cursor Raw Interrupt Status register . . . . . . 562
Cursor Masked Interrupt Status register . . . 562
SCT configuration register . . . . . . . . . . . . . . 593
SCT control register . . . . . . . . . . . . . . . . . . . 594
SCT limit register . . . . . . . . . . . . . . . . . . . . . 595
SCT halt condition register . . . . . . . . . . . . . . 596
SCT stop condition register . . . . . . . . . . . . . 596
SCT start condition register . . . . . . . . . . . . . 597
SCT counter register . . . . . . . . . . . . . . . . . . 597
SCT state register. . . . . . . . . . . . . . . . . . . . . 598
SCT input register. . . . . . . . . . . . . . . . . . . . . 598
SCT match/capture registers mode register . 599
SCT output register . . . . . . . . . . . . . . . . . . . 600
SCT bidirectional output control register. . . . 600
SCT conflict resolution register. . . . . . . . . . . 602
SCT DMA request 0 and 1 registers. . . . . . . 604
SCT flag enable register . . . . . . . . . . . . . . . . 605
SCT event flag register . . . . . . . . . . . . . . . . . 605
SCT conflict enable register . . . . . . . . . . . . . 606
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
23.7
23.7.1
23.7.1.1
23.7.1.2
23.7.2
23.7.3
23.7.4
23.7.5
23.7.5.1
23.7.5.2
23.7.5.3
23.7.5.4
23.7.5.5
23.7.5.6
23.7.6
23.7.7
23.7.8
23.7.9
23.7.10
23.7.10.1 STN displays . . . . . . . . . . . . . . . . . . . . . . . . 577
23.7.10.2 TFT displays . . . . . . . . . . . . . . . . . . . . . . . . 577
23.7.11
23.7.11.1 Master bus error interrupt . . . . . . . . . . . . . . 578
23.7.11.2 Vertical compare interrupt . . . . . . . . . . . . . . 578
23.7.11.2.1 Next base address update interrupt . . . . . . 578
23.7.11.2.2 FIFO underflow interrupt . . . . . . . . . . . . . . 578
23.7.12
23.8
23.9
24.6.18
24.6.19
24.6.20
24.6.21
24.6.22
24.6.23
24.6.24
24.6.25
24.6.26
24.7
24.7.1
24.7.2
24.7.3
24.7.4
24.7.5
24.7.6
24.7.7
24.7.8
24.7.9
LCD controller functional description. . . . . 563
LCD timing diagrams . . . . . . . . . . . . . . . . . . 581
LCD panel signal usage . . . . . . . . . . . . . . . . 583
Functional description . . . . . . . . . . . . . . . . . . 611
AHB interfaces . . . . . . . . . . . . . . . . . . . . . . . 564
AMBA AHB slave interface . . . . . . . . . . . . . 564
AMBA AHB master interface . . . . . . . . . . . . 564
Dual DMA FIFOs and associated control logic . .
565
Pixel serializer . . . . . . . . . . . . . . . . . . . . . . . 565
RAM palette . . . . . . . . . . . . . . . . . . . . . . . . . 569
Hardware cursor . . . . . . . . . . . . . . . . . . . . . 571
Cursor operation . . . . . . . . . . . . . . . . . . . . . 571
Cursor sizes . . . . . . . . . . . . . . . . . . . . . . . . . 572
Cursor movement . . . . . . . . . . . . . . . . . . . . 572
Cursor XY positioning . . . . . . . . . . . . . . . . . 572
Cursor clipping . . . . . . . . . . . . . . . . . . . . . . . 573
Cursor image format . . . . . . . . . . . . . . . . . . 574
Gray scaler. . . . . . . . . . . . . . . . . . . . . . . . . . 576
Upper and lower panel formatters . . . . . . . . 576
Panel clock generator . . . . . . . . . . . . . . . . . 577
Timing controller. . . . . . . . . . . . . . . . . . . . . . 577
STN and TFT data select . . . . . . . . . . . . . . . 577
Interrupt generation . . . . . . . . . . . . . . . . . . . 577
LCD power-up and power-down sequence . 578
SCT conflict flag register . . . . . . . . . . . . . . . 606
SCT match registers 0 to 15 (REGMODEn bit = 0)
606
SCT capture registers 0 to 15 (REGMODEn bit =
1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
SCT match reload registers 0 to 15 (REGMODEn
bit = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
SCT capture control registers 0 to 15
(REGMODEn bit = 1) . . . . . . . . . . . . . . . . . . 608
SCT event state mask registers 0 to 15 . . . . 608
SCT event control registers 0 to 15 . . . . . . . 608
SCT output set registers 0 to 15 . . . . . . . . . 610
SCT output clear registers 0 to 15 . . . . . . . . 610
Match logic. . . . . . . . . . . . . . . . . . . . . . . . . . . 611
Capture logic . . . . . . . . . . . . . . . . . . . . . . . . . 611
Event selection. . . . . . . . . . . . . . . . . . . . . . . . 611
Output generation . . . . . . . . . . . . . . . . . . . . 612
Interrupt generation . . . . . . . . . . . . . . . . . . . 612
Clearing the prescaler . . . . . . . . . . . . . . . . . 613
Match vs. I/O events . . . . . . . . . . . . . . . . . . 613
DMA operation . . . . . . . . . . . . . . . . . . . . . . . 614
Alternate addressing for match/capture registers
614
Chapter 43: Supplementary information
UM10430
© NXP B.V. 2011. All rights reserved.
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