LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 266

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
16.5.1 DMA request signals
16.5.2 DMA response signals
Table 195. Peripheral connections to the DMA controller and matching flow control signals
In addition to the peripherals listed in
can be accessed by the GPDMA as a memory-to-memory transaction with no flow control.
The DMA request signals are used by peripherals to request a data transfer. The DMA
request signals indicate whether a single or burst transfer of data is required and whether
the transfer is the last in the data packet. The DMA available request signals are:
BREQ[15:0] — Burst request signals. These cause a programmed burst number of data
to be transferred.
SREQ[15:0] — Single transfer request signals. These cause a single data to be
transferred. The DMA controller transfers a single transfer to or from the peripheral.
LBREQ[15:0] — Last burst request signals.
LSREQ[15:0] — Last single transfer request signals.
Note that most peripherals do not support all request types.
The DMA response signals indicate whether the transfer initiated by the DMA request
signal has completed. The response signals can also be used to indicate whether a
complete packet has been transferred. The DMA response signals from the DMA
controller are:
CLR[15:0] — DMA clear or acknowledge signals. The CLR signal is used by the DMA
controller to acknowledge a DMA request from the peripheral.
TC[15:0] — DMA terminal count signals. The TC signal can be used by the DMA
controller to indicate to the peripheral that the DMA transfer is complete.
Peripheral
Number
13
14
15
DMA
muxing
option
(see
Table
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
All information provided in this document is subject to legal disclaimers.
35)
Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller
Rev. 00.13 — 20 July 2011
SREQ
n.c.
n.c.
SSP1 receive
n.c.
n.c.
n.c.
SSP1 transmit
n.c.
n.c.
<tbd>SCT match 3
Reserved
n.c.
Table
195, the GPIOs, the WWDT, and the timers
BREQ
ADC0
AES input
SSP1 receive
USART3 receive
ADC1
AES output
SSP1 transmit
USART3 transmit
DAC
<tbd>
Reserved
Timer3 match 0
UM10430
© NXP B.V. 2011. All rights reserved.
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