LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 310

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
18.6.18 Raw Interrupt Status Register (RINTSTS)
Table 241. Masked Interrupt Status Register (MINTSTS, address 0x4000 4040) bit description
Table 242. Raw Interrupt Status Register (RINTSTS, address 0x4000 4044) bit description
Bit
5
6
7
8
9
10
11
12
13
14
15
31:16
Bit
0
1
2
3
Symbol
CD
RE
CD
DTO
Symbol
RXDR
RCRC
DCRC
RTO
DRTO
HTO
FRUN
HLE
SBE
ACD
EBE
SDIO_INTERR
UPT
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Description
Receive FIFO data request. Interrupt enabled only if
corresponding bit in interrupt mask register is set.
Response CRC error. Interrupt enabled only if
corresponding bit in interrupt mask register is set.
Data CRC error. Interrupt enabled only if corresponding bit
in interrupt mask register is set.
Response time-out. Interrupt enabled only if corresponding
bit in interrupt mask register is set.
Data read time-out. Interrupt enabled only if corresponding
bit in interrupt mask register is set.
Data starvation-by-host time-out (HTO). Interrupt enabled
only if corresponding bit in interrupt mask register is set.
FIFO underrun/overrun error. Interrupt enabled only if
corresponding bit in interrupt mask register is set.
Hardware locked write error. Interrupt enabled only if
corresponding bit in interrupt mask register is set.
Start-bit error. Interrupt enabled only if corresponding bit in
interrupt mask register is set.
Auto command done. Interrupt enabled only if
corresponding bit in interrupt mask register is set.
End-bit error (read)/write no CRC. Interrupt enabled only if
corresponding bit in interrupt mask register is set.
Interrupt from SDIO card; one bit for each card. Bit[31]
corresponds to Card[15], and bit[16] is for Card[0]. SDIO
interrupt for card enabled only if corresponding
sdio_int_mask bit is set in Interrupt mask register (mask bit
1 enables interrupt; 0 masks interrupt).
0 - No SDIO interrupt from card
1 - SDIO interrupt from card In MMC-Ver3.3-only mode,
bits always 0.
Description
Card detect. Writes to bits clear status bit. Value of 1 clears
status bit, and value of 0 leaves bit intact. Bits are logged
regardless of interrupt mask status.
Response error. Writes to bits clear status bit. Value of 1
clears status bit, and value of 0 leaves bit intact. Bits are
logged regardless of interrupt mask status.
Command done. Writes to bits clear status bit. Value of 1
clears status bit, and value of 0 leaves bit intact. Bits are
logged regardless of interrupt mask status.
Data transfer over. Writes to bits clear status bit. Value of 1
clears status bit, and value of 0 leaves bit intact. Bits are
logged regardless of interrupt mask status.
Chapter 18: LPC18xx SD/MMC interface
UM10430
© NXP B.V. 2011. All rights reserved.
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