LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 908

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
39.6 Functional description
<Document ID>
User manual
39.5.3 D/A Converter Counter Value register
39.6.1 DMA counter
39.6.2 Double buffering
Table 838. D/A Control register (CTRL - address 0x400E 1004) bit description
This read/write register contains the reload value for the Interrupt/DMA counter.
Table 839: D/A Converter counter value register (CNTVAL - address 0x400E 1008) bit
When the counter enable bit CNT_ENA in DACCTRL is set, a 16-bit counter will begin
counting down, at the rate selected by CLK_APB3_DAC, from the value programmed into
the DACCNTVAL register. The counter is decremented Each time the counter reaches
zero, the counter will be reloaded by the value of DACCNTVAL and the DMA request bit
INT_DMA_REQ will be set in hardware.
Note that the contents of the DACCTRL and DACCNTVAL registers are read and write
accessible, but the timer itself is not accessible for either read or write.
If the DMA_ENA bit is set in the DACCTRL register, the DAC DMA request will be routed
to the GPDMA. When the DMA_ENA bit is cleared, the default state after a reset, DAC
DMA requests are blocked.
Double-buffering is enabled only if both, the CNT_ENA and the DBLBUF_ENA bits are set
in DACCTRL. In this case, any write to the DACR register will only load the pre-buffer,
which shares its register address with the DACR register. The DACR itself will be loaded
from the pre-buffer whenever the counter reaches zero and the DMA request is set. At the
same time the counter is reloaded with the COUNTVAL register value.
Reading the DACR register will only return the contents of the DACR register itself, not the
contents of the pre-buffer register.
Bit
2
3
31:4
Bit
15:0
31:16 -
Symbol
CNT_ENA
DMA_ENA
-
Symbol
VALUE
description
All information provided in this document is subject to legal disclaimers.
Description
16-bit reload value for the DAC interrupt/DMA timer.
Reserved.
Rev. 00.13 — 20 July 2011
Value Description
0
1
0
1
DMA time-out
Time-out counter operation is disabled.
Time-out counter operation is enabled.
DMA enable
DMA access is disabled.
DMA Burst Request Input 15 is enabled for the DAC (see
Table
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
195).
Chapter 39: LPC18xx DAC
UM10430
© NXP B.V. 2011. All rights reserved.
Reset value
0
-
908 of 1164
Reset
value
0
0
-