LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 778

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
34.7 Functional description
<Document ID>
User manual
Fig 100. Texas Instruments Synchronous Serial Frame Format: a) Single and b) Continuous/back-to-back Two
a. Single frame transfer
b. Continuous/back-to-back frames transfer
Frames Transfer
DX/DR
CLK
34.7.1 Texas Instruments synchronous serial frame format
FS
Table 725: SSP DMA Control Register (DMACR - address 0x4008 3024 (SSP0), 0x400C 5024
Figure 100
supported by the SSP module.
For device configured as a master in this mode, CLK and FS are forced LOW, and the
transmit data line DX is tri-stated whenever the SSP is idle. Once the bottom entry of the
transmit FIFO contains data, FS is pulsed HIGH for one CLK period. The value to be
transmitted is also transferred from the transmit FIFO to the serial shift register of the
transmit logic. On the next rising edge of CLK, the MSB of the 4-bit to 16-bit data frame is
shifted out on the DX pin. Likewise, the MSB of the received data is shifted onto the DR
pin by the off-chip serial slave device.
Bit
0
1
31:2
DX/DR
CLK
FS
Symbol
RXDMAE
TXDMAE
-
MSB
(SSP1)) bit description
shows the 4-wire Texas Instruments synchronous serial frame format
All information provided in this document is subject to legal disclaimers.
4 to 16 bits
Rev. 00.13 — 20 July 2011
MSB
Description
Receive DMA Enable. When this bit is set to one 1, DMA
for the receive FIFO is enabled, otherwise receive DMA is
disabled.
Transmit DMA Enable. When this bit is set to one 1, DMA
for the transmit FIFO is enabled, otherwise transmit DMA
is disabled
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
LSB
4 to 16 bits
MSB
LSB
4 to 16 bits
Chapter 34: LPC18xx SSP0/1
LSB
UM10430
© NXP B.V. 2011. All rights reserved.
778 of 1164
Reset
value
0
0
NA