LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 246

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
15.3 Features
15.4 Introduction
<Document ID>
User manual
15.3.1 GPIO pin interrupt features
15.3.2 GPIO group interrupt features
15.3.3 GPIO port features
15.4.1 GPIO pin interrupts
15.4.2 GPIO group interrupt
The GPIO pins can be used in several ways to set pins as inputs or outputs and use the
inputs as combinations of level and edge sensitive interrupts.
From all available GPIO pins, up to eight pins can be selected in the system control block
to serve as external interrupt pins (see <tbd>). The external interrupt pins are connected
to eight individual interrupts in the NVIC and are created based on rising or falling edges
or on the input level on the pin.
For each port/pin connected to one of the two the GPIO Grouped Interrupt blocks
(GROUP0 and GROUP1), the GPIO grouped interrupt registers determine which pins are
enabled to generate interrupts and what the active polarities of each of those inputs are.
The GPIO grouped interrupt registers also select whether the interrupt output will be level
or edge triggered and whether it will be based on the OR or the AND of all of the enabled
inputs.
•
•
•
•
•
•
•
•
•
•
•
Up to 8 pins can be selected from all GPIO pins as edge- or level-sensitive interrupt
requests. Each request creates a separate interrupt in the NVIC.
Edge-sensitive interrupt pins can interrupt on rising or falling edges or both.
Level-sensitive interrupt pins can be HIGH- or LOW-active.
The inputs from any number of GPIO pins can be enabled to contribute to a combined
group interrupt.
The polarity of each input enabled for the group interrupt can be configured HIGH or
LOW.
Enabled interrupts can be logically combined through an OR or AND operation.
Two group interrupts are supported to reflect two distinct interrupt patterns.
The GPIO group interrupts can wake up the part from sleep, deep-sleep or
power-down modes.
GPIO pins can be configured as input or output by software.
All GPIO pins default to inputs with interrupt disabled at reset.
Pin registers allow pins to be sensed and set individually.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 15: LPC18xx GPIO
UM10430
© NXP B.V. 2011. All rights reserved.
246 of 1164