LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1124

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 105. Reset external status registers x
Table 106. Reset external status registers y
Table 107. Pin description . . . . . . . . . . . . . . . . . . . . . . .135
Table 108. SCU clocking and power control . . . . . . . . . .185
Table 109. Pin multiplexing . . . . . . . . . . . . . . . . . . . . . . .187
Table 110. Register overview: System Control Unit (SCU)
Table 111. Pin configuration for normal drive pins P0_n to
Table 112. Pin configuration for high drive pins P0_n to PF_n
Table 113. Pins controlled by the ENAIO0 register . . . . .207
Table 114. ADC0 function select register (ENAIO0, address
Table 115. Pins controlled by the ENAIO1 register . . . . .208
Table 116. ADC1 function select register (ENAIO1, address
Table 117. Pins controlled by the ENAIO2 register . . . . .209
Table 118. Analog function select register (ENAIO2, address
Table 119. Pin configuration for pins DP1/DM1 register
Table 120. Pin configuration for open-drain I
Table 121. EMC clock delay register (EMCCLKDELAY,
Table 122. EMC control delay register (EMCCTRLDELAY,
Table 123. EMC chip select delay register (EMCCSDELAY,
Table 124. EMC data out delay register (EMCDOUTDELAY,
Table 125. EMC DQM delay register (EMCFBCLKDELAY,
Table 126. EMC address delay register 0
Table 127. EMC address delay register 1
Table 128. EMC address delay register 2
Table 129. EMC data in delay register 3 (EMCDINDELAY,
Table 130. Pin interrupt select register 0 (PINTSEL0,
<Document ID>
User manual
description . . . . . . . . . . . . . . . . . . . . . . . . . .132
(RESET_EXT_STATx, address 0x4005 34xx) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . .133
(RESET_EXT_STATy, address 0x4005 34yy) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . .133
(base address 0x4008 6000)
PF_n and CLK0 to CLK3 registers (SFS, address
0x4008 6000 (SPSP0_0) to 0x4008 6C0C
(SFSCLK3)) bit description . . . . . . . . . . . . . .205
and CLK0 to CLK3 registers (SFS, address
0x4008 6000 (SFSP0_0) to 0x4008 6C0C
(SFSCLK3) bit description . . . . . . . . . . . . . .206
0x4008 6C88) bit description . . . . . . . . . . . .207
0x4008 6C8C) bit description . . . . . . . . . . . .208
0x4008 6C90) bit description . . . . . . . . . . . .210
(SFSUSB, address 0x4008 6C80) bit description
210
register (SFSI2C0, address 0x4008 6C84) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . .210
address 0x4008 6D00) bit description . . . . . 211
address 0x4008 6D04) bit description . . . . .212
address 0x4008 6D08) bit description . . . . .212
address 0x4008 6D0C) bit description . . . . .213
address 0x4008 6D10) bit description . . . . .214
(EMCADDRDELAY0, address 0x4008 6D14) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . .214
(EMCADDRDELAY1, address 0x4008 6D18) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . .215
(EMCADDRDELAY2, address 0x4008 6D1C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . .215
address 0x4008 6D24) bit description . . . . .216
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
All information provided in this document is subject to legal disclaimers.
2
C-bus pins
Rev. 00.13 — 20 July 2011
Table 131. Pin interrupt select register 1 (PINTSEL1,
Table 132. GIMA clocking and power control . . . . . . . . . 220
Table 133. GIMA inputs . . . . . . . . . . . . . . . . . . . . . . . . . 220
Table 134. Register overview: GIMA (base address: 0x400C
Table 135. Timer 0 CAP0_0 capture input multiplexer
Table 136. Timer 0 CAP0_1 capture input multiplexer
Table 137. Timer 0 CAP0_2 capture input multiplexer
Table 138. Timer 0 CAP0_3 capture input multiplexer
Table 139. Timer 1 CAP1_0 capture input multiplexer
Table 140. Timer 1 CAP1_1 capture input multiplexer
Table 141. Timer 1 CAP1_2 capture input multiplexer
Table 142. Timer 1 CAP1_3 capture input multiplexer
Table 143. Timer 2 CAP2_0 capture input multiplexer
Table 144. Timer 2 CAP2_1 capture input multiplexer
Table 145. Timer 2 CAP2_2 capture input multiplexer
Table 146. Timer 2 CAP2_3 capture input multiplexer
Table 147. Timer 3 CAP3_0 capture input multiplexer
Table 148. Timer 3 CAP3_1 capture input multiplexer
Table 149. Timer 3 CAP3_2 capture input multiplexer
Table 150. Timer 3 CAP3_3 capture input multiplexer
Table 151. SCT CTIN_0 capture input multiplexer
address 0x4008 6E00) bit description . . . . . . 217
address 0x4008 6E04) bit description . . . . . . 218
7000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
(CAP0_0_IN, address 0x400C 7000) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
(CAP0_1_IN, address 0x400C 7004) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
(CAP0_2_IN, address 0x400C 7008) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
(CAP0_3_IN, address 0x400C 700C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
(CAP1_0_IN, address 0x400C 7010) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
(CAP1_1_IN, address 0x400C 7014) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
(CAP1_2_IN, address 0x400C 7018) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
(CAP1_3_IN, address 0x400C 701C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
(CAP2_0_IN, address 0x400C 7020) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
(CAP2_1_IN, address 0x400C 7024) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
(CAP2_2_IN, address 0x400C 7028) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
(CAP2_3_IN, address 0x400C 702C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
(CAP3_0_IN, address 0x400C 7030) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
(CAP3_1_IN, address 0x400C 7034) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
(CAP3_2_IN, address 0x400C 7038) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
(CAP3_3_IN, address 0x400C 703C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
(CTIN_0_IN, address 0x400C 7040) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Chapter 43: Supplementary information
UM10430
© NXP B.V. 2011. All rights reserved.
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