LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 865

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
37.8 I
<Document ID>
User manual
2
C operating modes
37.8.1 Master Transmitter mode
Table 813. I
In a given application, the I
mode, the I
address. If one of these addresses is detected, an interrupt is requested. If the processor
wishes to become the bus master, the hardware waits until the bus is free before the
master mode is entered so that a possible slave operation is not interrupted. If bus
arbitration is lost in the master mode, the I
immediately and can detect its own slave address in the same serial transfer.
In this mode data is transmitted from master to slave. Before the master transmitter mode
can be entered, the CONSET register must be initialized as shown in
must be set to 1 to enable the I
acknowledge any address when another device is master of the bus, so it can not enter
slave mode. The STA, STO and SI bits must be 0. The SI Bit is cleared by writing 1 to the
SIC bit in the CONCLR register. The STA bit should be cleared after writing the slave
address.
Table 814. CONSET used to configure Master mode
The first byte transmitted contains the slave address of the receiving device (7 bits) and
the data direction bit. In this mode the data direction bit (R/W) should be 0 which means
Write. The first byte transmitted contains the slave address and Write bit. Data is
transmitted 8 bits at a time. After each byte is transmitted, an acknowledge bit is received.
START and STOP conditions are output to indicate the beginning and the end of a serial
transfer.
The I
I
condition is transmitted, the SI bit is set, and the status code in the STAT register is 0x08.
This status code is used to vector to a state service routine which will load the slave
address and Write bit to the DAT register, and then clear the SI bit. SI is cleared by writing
a 1 to the SIC bit in the CONCLR register.
Bit
0
7:1
31:8 -
2
Bit
Symbol
Value
C logic will send the START condition as soon as the bus is free. After the START
2
C interface will enter master transmitter mode when software sets the STA bit. The
Symbol
-
MASK
(MASK3) (I2C0) and 0x400E 0030 (MASK0) to 0x400E 003C (MASK3) (I2C1)) bit
description
7
-
-
2
2
C hardware looks for any one of its four slave addresses and the General Call
C Mask registers (MASK - address 0x400A 1030 (MASK0) to 0x400A 103C
All information provided in this document is subject to legal disclaimers.
Description
Reserved. User software should not write ones to reserved bits.
This bit reads always back as 0.
Mask bits.
Reserved. The value read from a reserved bit is not defined.
6
I2EN
1
Rev. 00.13 — 20 July 2011
2
C block may operate as a master, a slave, or both. In the slave
5
STA
0
2
C function. If the AA bit is 0, the I
4
STO
0
2
C block switches to the slave mode
Chapter 37: LPC18xx I2C-bus interface
3
SI
0
2
AA
0
2
C interface will not
Table
UM10430
-
1
-
© NXP B.V. 2011. All rights reserved.
814. I2EN
Reset value
0
0x00
-
865 of 1164
0
-
-