LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1123

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 61. PLL1_CTRL register (PLL1_CTRL, address
Table 62. IDIVA control register (IDIVA_CTRL, address
Table 63. IDIVB/C/D control registers (IDIVB_CTRL,
Table 64. IDIVE control register (IDIVE_CTRL, address
Table 65. Output stage 0 control register
Table 66. Output stage 1 control register
Table 67. Output stage 3 control register
Table 68. Output stage 4 to 19 control registers
Table 69. Output stage 20 control register
Table 70. Output stage 25 control register
Table 71. Output stage 26 to 27 control register
Table 72. PLL operating modes . . . . . . . . . . . . . . . . . . .92
Table 73. DIRECTL and DIRECTO bit settings in
Table 74. System PLL divider ratio settings for 12 MHz. .94
Table 75. CCU clocking and power control . . . . . . . . . . .99
Table 76. CCU1 branch clocks . . . . . . . . . . . . . . . . . . . . .99
Table 77. CCU2 branch clocks . . . . . . . . . . . . . . . . . . . .101
Table 78. Register overview: CCU1 (base address 0x4005
Table 79. Register overview: CCU2 (base address 0x4005
Table 80. CCU1/2 power mode register (CCU1_PM,
Table 81. CCU1 base clock status register
Table 82. CCU2 base clock status register
Table 83. CCU1 branch clock configuration register
<Document ID>
User manual
0x4005 0040) bit description . . . . . . . . . . . . . .79
0x4005 0044) bit description
0x4005 0048) bit description
address 0x4005 004C; IDIVC_CTRL, address
0x4005 0050; IDIVC_CTRL, address 0x4005
0054) bit description . . . . . . . . . . . . . . . . . . . .82
0x4005 0058) bit description
(OUTCLK_0_CTRL, address 0x4005 005C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .84
(OUTCLK_1_CTRL, address 0x4005 0060) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .85
(OUTCLK_3_CTRL, address 0x4005 0068) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .85
(OUTCLK_4_CTRL to OUTCLK_19_CTRL,
address 0x4005 006C to 0x4005 00A8) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .86
(OUTCLK_20_CTRL, addresses 0x4005 00AC)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .87
(OUTCLK_25_CTRL, addresses 0x4005 00C0)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .88
(OUTCLK_26_CTRL to OUTCLK_27_CTRL,
addresses 0x4005 00C4 to 0x4005 00C8) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .89
HP0/1_Mode register . . . . . . . . . . . . . . . . . . . .92
1000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
2000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
address 0x4005 1000 and CCU2_PM, address
0x4005 2000) bit description . . . . . . . . . . . . .106
(CCU1_BASE_STAT, address 0x4005 1004) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .106
(CCU2_BASE_STAT, address 0x4005 2004) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .107
(CLK_XXX_CFG, addresses 0x4005 1100,
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
. . . . . . . . . . . . .83
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Table 84. CCU1 branch clock configuration register
Table 85. CCU2 branch clock configuration register
Table 86. CCU1 branch clock status register
Table 87. CCU2 branch clock status register
Table 88. RGU clocking and power control . . . . . . . . . . 111
Table 89. Reset output configuration . . . . . . . . . . . . . . 112
Table 90. Reset priority . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 91. Register overview: RGU (base address: 0x4005
Table 92. Reset control register 0 (RESET_CTRL0, address
Table 93. Reset control register 1 (RESET_CTRL1, address
Table 94. Reset status register 0 (RESET_STATUS0,
Table 95. Reset status register 1 (RESET_STATUS1,
Table 96. Reset status register 2 (RESET_STATUS2,
Table 97. Reset status register 3 (RESET_STATUS3,
Table 98. Reset active status register 0
Table 99. Reset active status register 1
Table 100. Reset external status register 0
Table 101. Reset external status register 1
Table 102. Reset external status register 2
Table 103. Reset external status register 4
Table 104. Reset external status register 5
0x4005 1104,..., 0x4005 1A00) bit description . .
108
(CLK_EMCDIV_CFG, addresses 0x4005 1478)
bit description . . . . . . . . . . . . . . . . . . . . . . . . 108
(CLK_XXX_CFG, addresses 0x4005 2100,
0x4005 2200,..., 0x4005 2800) bit description . .
109
(CLK_XXX_STAT, addresses 0x4005 1104,
0x4005 110C,..., 0x4005 1A04) bit description . .
109
(CLK_XXX_STAT, addresses 0x4005 2104,
0x4005 2204,..., 0x4005 2804) bit description . .
110
3000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
0x4005 3100) bit description . . . . . . . . . . . . 118
0x4005 3104) bit description
address 0x4005 3110) bit description . . . . . . 121
address 0x4005 3114) bit description
address 0x4005 3118) bit description
address 0x4005 311C) bit description
(RESET_ACTIVE_STATUS0, address 0x4005
3150) bit description . . . . . . . . . . . . . . . . . . . 127
(RESET_ACTIVE_STATUS1, address 0x4005
3154) bit description . . . . . . . . . . . . . . . . . . . 129
(RESET_EXT_STAT0, address 0x4005 3400) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . 131
(RESET_EXT_STAT1, address 0x4005 3404) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . 132
(RESET_EXT_STAT2, address 0x4005 3408) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . 132
(RESET_EXT_STAT4, address 0x4005 3410) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . 132
(RESET_EXT_STAT5, address 0x4005 3414) bit
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Chapter 43: Supplementary information
UM10430
© NXP B.V. 2011. All rights reserved.
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