LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 510

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
Fig 45. Wake-up frame filter register
WKUPFMFILTER0
WKUPFMFILTER1
WKUPFMFILTER2
WKUPFMFILTER3
WKUPFMFILTER4
WKUPFMFILTER5
WKUPFMFILTER6
WKUPFMFILTER7
22.7.1.1 Remote wake-up frame registers
22.7.1 Power management block
This section describes the power management (PMT) mechanisms supported by the
MAC. PMT supports the reception of network (remote) wake-up frames and Magic Packet
frames. PMT does not perform the clock gate function, but generates interrupts for
wake-up frames and Magic Packets received by the MAC. The PMT block sits on the
receiver path of the MAC and is enabled with remote wake-up frame enable and Magic
Packet enable. These enables are in the PMT Control and Status register and are
programmed by the Application.
When the power-down mode is enabled in the PMT, then all received frames are dropped
by the core and they are not forwarded to the application. The core comes out of the
power down mode only when either a Magic Packet or a Remote Wake-up frame is
received and the corresponding detection is enabled.
The register wkupfmfilter_reg, address (0x028), loads the Wake-up Frame Filter register.
To load values in a Wake-up Frame Filter register, the entire register
(WKUPFMFILTER_REG) must be written. The WKUPFMFILTER_REG register is loaded
by sequentially loading the eight register values in address (0x028) for
WKUPFMFILTER_REG0, WKUPFMFILTER_REG1,... WKUPFMFILTER_REG7,
respectively. WKUPFMFILTER_REG is read in the same way.
Remark: The internal counter to access the appropriate WKUPFMFILTER_REG is
incremented when lane 3 (or lane 0 in big-endian) is accessed by the CPU. This should be
kept in mind if you are accessing these registers in byte or half-word mode.
Filter i byte mask
RSVD
Filter 3 Offset
Command
Filter 3
Filter 1 CRC - 16
Filter 3 CRC - 16
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
RSVD
Filter 2 Offset
Command
Filter 2
Filter 0 Byte Mask
Filter 1 Byte Mask
Filter 2 Byte Mask
Filter 3 Byte Mask
RSVD
Filter 1 Offset
Command
Chapter 22: LPC18xx Ethernet
Filter 1
Filter 0 CRC - 16
Filter 2 CRC - 16
RSVD
UM10430
Filter 0 Offset
© NXP B.V. 2011. All rights reserved.
Command
Filter 0
510 of 1164