LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 804

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
Fig 120. Receiver slave mode sharing the transmitter reference clock
Fig 121. 4-wire receiver slave mode sharing the transmitter bit clock and WS
35.7.3 FIFO controller
TX_REF
Handling of data for transmission and reception is performed via the FIFO controller which
can generate two DMA requests and an interrupt request. The controller consists of a set
of comparators which compare FIFO levels with depth settings contained in registers. The
current status of the level comparators can be seen in the APB status register.
Table 746. Conditions for FIFO level comparison
System signaling occurs when a level detection is true and enabled.
Table 747. DMA and interrupt request generation
Table 748. Status feedback in the STATE register
Level Comparison
dmareq_tx_1
dmareq_rx_1
dmareq_tx_2
dmareq_rx_2
irq_tx
irq_rx
System Signaling
irq
dmareq[0]
dmareq[1]
Status Feedback
irq
dmareq1
dmareq2
I2SRXBITRATE[5:0]
TX bit clock
(1 to 64)
÷N
All information provided in this document is subject to legal disclaimers.
RX bit clock
peripheral
(receive)
Rev. 00.13 — 20 July 2011
block
I
2
S
Condition
tx_depth_dma1 >= tx_level
rx_depth_dma1 <= rx_level
tx_depth_dma2 >= tx_level
rx_depth_dma2 <= rx_level
tx_depth_irq >= tx_level
rx_depth_irq <= rx_level
Condition
(irq_rx & rx_irq_enable) | (irq_tx & tx_irq_enable)
(dmareq_tx_1 & tx_dma1_enable ) | (dmareq_rx_1 &
rx_dma1_enable )
( dmareq_tx_2 & tx_dma2_enable ) | (dmareq_rx_2 &
rx_dma2_enable )
Status
irq_rx | irq_tx
(dmareq_tx_1 | dmareq_rx_1)
(dmareq_rx_2 | dmareq_tx_2)
peripheral
(receive)
block
TX_WS ref
I
2
S
I2S_RX_SDA
Chapter 35: LPC18xx I2S interface
I2S_RX_SDA
I2S_RX_WS
UM10430
© NXP B.V. 2011. All rights reserved.
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