LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1011

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 955. Register overview: CCU2 (base address 0x4005 2000)
<Document ID>
User manual
Name
CLK_APB2_USART3_STAT
-
CLK_APB2_USART2_CFG
CLK_APB2_USART2_STAT
-
CLK_APB0_UART1_CFG
CLK_APB0_UART1_STAT
-
CLK_APB0_USART0_CFG
CLK_APB0_USART0_STAT
-
CLK_APB2_SSP1_CFG
CLK_APB2_SSP1_STAT
-
CLK_APB0_SSP0_CFG
CLK_APB0_SSP0_STAT
-
CLK_SDIO_CFG
CLK_SDIO_STAT
42.5.5.1 Power mode register
This register contains a single bit, PD, that when set will disable all output clocks with
Wake-up enabled (i.e. W = 1 in the CCU branch clock configuration registers,
Section
wake-up interrupt is detected or when a 0 is written into the PD bit.
Table 956. CCU1/2 power mode register (CCU1_PM, address 0x4005 1000 and CCU2_PM,
Bit
0
31:1
Symbol
PD
-
42.5.5.3). Clocks disabled by writing to this register will be reactivated when a
address 0x4005 2000) bit description
Access
R
-
R/W
R
-
R/W
R
-
R/W
R
-
R/W
R
-
R/W
R
-
R/W
R
All information provided in this document is subject to legal disclaimers.
Value
0
1
Address
offset
0x204
0x208 to
0x2FC
0x300
0x304
0x308 to
0x3FC
0x400
0x404
0x408 to
0x4FC
0x500
0x504
0x508 to
0x5FC
0x600
0x604
0x608 to
0x6FC
0x700
0x704
0x708 to
0x7FC
0x800
0x804
Rev. 00.13 — 20 July 2011
Description
Initiate power-down mode
Normal operation.
Clocks with wake-up mode enabled (W = 1) are
disabled.
Reserved.
Description
CLK_APB2_UART3 status register
Reserved
CLK_APB2_UART2 configuration register
CLK_APB2_UART2 status register
Reserved
CLK_APB0_UART1 configuration register
CLK_APB0_UART1 status register
Reserved
CLK_APB0_UART0 configuration register
CLK_APB0_UART0 status register
Reserved
CLK_APB2_SSP1 configuration register
CLK_APB2_SSP1 status register
Reserved
CLK_APB0_SSP0 configuration register
CLK_APB0_SSP0 status register
Reserved
CLK_SDIO configuration register
CLK_SDIO status register
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
-
Reset value
0x0000 0001
-
0x0000 0001
0x0000 0001
-
0x0000 0001
0x0000 0001
-
0x0000 0001
0x0000 0001
-
0x0000 0001
0x0000 0001
-
0x0000 0001
0x0000 0001
-
0x0000 0001
0x0000 0001
1011 of 1164
Access
R/W
-