LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 936

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
41.6 Debug Notes
<Document ID>
User manual
Table 881. JTAG pin description
Table 882. Serial Wire Debug pin description
Table 883. Parallel Trace pin description
Important: The user should be aware of certain limitations during debugging. The most
important is that, due to limitations of the Cortex-M3 integration, the LPC18xx cannot
wake up in the usual manner from Deep Sleep and Power-down modes. It is
recommended not to use these modes during debug.
Another issue is that debug mode changes the way in which reduced power modes are
handled by the Cortex-M3 CPU. This causes power modes at the device level to be
different from normal modes operation. These differences mean that power
measurements should not be made while debugging, the results will be higher than during
normal operation in an application.
Pin Name
TCK
TMS
TDI
TDO
TRST
Pin Name
SWDCLK
SWDIO
SWO
Pin Name
TRACECLK
TRACEDATA[3:0] Output
All information provided in this document is subject to legal disclaimers.
Type
Input
Input
Input
Output
Input
Type
Input
Input /
Output
Output
Type
Input
Chapter 41: LPC18xx JTAG, Serial Wire Debug (SWD), and trace
Rev. 00.13 — 20 July 2011
Description
JTAG Test Clock. This pin is the clock for debug logic when in the
JTAG debug mode.
JTAG Test Mode Select. The TMS pin selects the next state in the
TAP state machine.
JTAG Test Data In. This is the serial data input for the shift register.
JTAG Test Data Output. This is the serial data output from the shift
register. Data is shifted out of the device on the negative edge of the
TCK signal.
JTAG Test Reset. The TRST pin can be used to reset the test logic
within the debug logic.
Description
Serial Wire Clock. This pin is the clock for debug logic when in the
Serial Wire Debug mode.
Serial wire debug data input/output. The SWDIO pin is used by an
external debug tool to communicate with and control the Cortex-M3
CPU.
Serial Wire Output. The SWO pin optionally provides data from the
ITM and/or the ETM for an external debug tool to evaluate.
Description
Trace Clock. This pin provides the sample clock for trace data on
the TRACEDATA pins when tracing is enabled by an external debug
tool.
Trace Data bits 3 to 0. These pins provide ETM trace data when
tracing is enabled by an external debug tool. The debug tool can
then interpret the compressed information and make it available to
the user.
UM10430
© NXP B.V. 2011. All rights reserved.
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