LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 242

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
14.4.27 Event router input 14 multiplexer (EVENTROUTER_14_IN)
Table 160. Event router input 13 multiplexer (EVENTROUTER_13_IN, address 0x400C 7064)
Table 161. Event router input 14 multiplexer (EVENTROUTER_14_IN, address 0x400C 7068)
Bit
1
2
3
7:4
31:8
Bit
0
1
2
3
7:4
31:8
Symbol
EDGE
SYNCH
PULSE
SELECT
-
Symbol
INV
EDGE
SYNCH
PULSE
SELECT
-
bit description
bit description
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
0
1
0
1
0x0
0x1
0x2
Value
0
1
0
1
0
1
0
1
0x0
0x1
0x2
Rev. 00.13 — 20 July 2011
Chapter 14: LPC18xx Global Input Multiplexer Array (GIMA)
Enable rising edge detection
No edge detection.
Rising edge detection enabled.
Enable synchronization
Disable synchronization.
Enable synchronization.
Enable single pulse generation.
Disable single pulse generation.
Enable single pulse generation.
Select input. Values 0x3 to 0xF are reserved.
CTOUT_2 or T0_MAT2
Reserved
T0_MAT2
Reserved
Enable rising edge detection
Select input. Values 0x3 to 0xF are reserved.
Description
Invert input
Not inverted.
Input inverted.
No edge detection.
Rising edge detection enabled.
Enable synchronization
Disable synchronization.
Enable synchronization.
Enable single pulse generation.
Disable single pulse generation.
Enable single pulse generation.
CTOUT_6 or T1_MAT2
Reserved
T1_MAT2
Reserved
UM10430
© NXP B.V. 2011. All rights reserved.
Reset value
Reset value
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