LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 740

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
Fig 92. Typical smart card application
LPCxxxx
32.6.4.1 Smart card set-up procedure
selectable
power rail
MATx/
PWMx
GPIO
GPIO
GPIO
TXD
When the SCIEN bit in the SCICTRL register
UART provides bidirectional serial data on the open-drain TXD pin. No RXD pin is used
when SCIEN is 1. If a clock source is needed as an oscillator source into the Smart Card,
a timer match or PWM output can be used in cases when a higher frequency clock is
needed that is not synchronous with the data bit rate. The UART SCLK pin will output
synchronously with the data and at the data bit rate and may not be adequate for most
asynchronous cards. Software must use timers to implement character and block waiting
times (no hardware support via trigger signals is provided on the LPCxxxx). GPIO pins
can be used to control the smart card reset and power pins. Any power supplied to the
card must be externally switched as card power supply requirements often exceed source
currents possible on the LPCxxxx. As the specific application may accommodate any of
the available ISO 7816 class A, B, or C power requirements, be aware of the logic level
tolerances and requirements when communicating or powering cards that use different
power rails than the LPCxxxx.
A T = 0 protocol transfer consists of 8-bits of data, an even parity bit, and two guard bits
that allow for the receiver of the particular transfer to flag parity errors through the NACK
response (see
requirements. If no NACK is sent (provided the interface accepts them in SCICTRL), the
next byte may be transmitted immediately after the last guard bit. If the NACK is sent, the
transmitter will retry sending the byte until successfully received or until the SCICTRL
retry limit has been met.
Figure
All information provided in this document is subject to legal disclaimers.
Logic Level
Translation
Optional
93). Extra guard bits may be added according to card
Rev. 00.13 — 20 July 2011
pull-up
resistor
pull-up
resistor
(Table
Chapter 32: LPC18xx USART0_2_3
681) is set as described above, the
pull-up
resistor
VCC
CLK
I/O
RST
Insertion Switch
UM10430
Smart Card
© NXP B.V. 2011. All rights reserved.
ISO 7816
740 of 1164