LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1150

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller
16.1
16.2
16.3
16.4
16.5
16.5.1
16.5.2
16.6
16.6.1
16.6.2
16.6.3
16.6.4
16.6.5
16.6.6
16.6.7
16.6.8
16.6.9
16.6.10
16.6.11
16.6.12
16.6.13
16.6.14
16.6.15
16.6.16
16.6.17
16.6.18
16.6.19
16.6.19.1 Protection and access information . . . . . . . . 278
16.6.20
16.6.20.1 Lock control . . . . . . . . . . . . . . . . . . . . . . . . . 281
16.6.20.2 Flow control and transfer type . . . . . . . . . . . 281
16.7
16.7.1
16.7.1.1
Chapter 17: LPC18xx SPI Flash Interface (SPIFI)
17.1
17.2
17.3
Chapter 18: LPC18xx SD/MMC interface
18.1
18.2
18.3
18.4
18.5
18.6
18.6.1
18.6.2
<Document ID>
User manual
How to read this chapter . . . . . . . . . . . . . . . . 263
Basic configuration . . . . . . . . . . . . . . . . . . . . 263
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
General description . . . . . . . . . . . . . . . . . . . . 264
DMA system connections . . . . . . . . . . . . . . . 264
Register description . . . . . . . . . . . . . . . . . . . 267
Functional description . . . . . . . . . . . . . . . . . 282
How to read this chapter . . . . . . . . . . . . . . . . 294
Basic configuration . . . . . . . . . . . . . . . . . . . . 294
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
How to read this chapter . . . . . . . . . . . . . . . . 296
Basic configuration . . . . . . . . . . . . . . . . . . . . 296
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
General description . . . . . . . . . . . . . . . . . . . . 296
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 297
Register description . . . . . . . . . . . . . . . . . . . 298
DMA request signals . . . . . . . . . . . . . . . . . . 266
DMA response signals . . . . . . . . . . . . . . . . . 266
DMA Interrupt Status Register . . . . . . . . . . . 268
DMA Interrupt Terminal Count Request Status
Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
DMA Interrupt Terminal Count Request Clear
Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
DMA Interrupt Error Status Register . . . . . . 269
DMA Interrupt Error Clear Register . . . . . . . 270
DMA Raw Interrupt Terminal Count Status
Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
DMA Raw Error Interrupt Status Register . . 271
DMA Enabled Channel Register . . . . . . . . . 271
DMA Software Burst Request Register . . . . 271
DMA Software Single Request Register . . . 272
DMA Software Last Burst Request Register 272
DMA Software Last Single Request Register 273
DMA Configuration Register . . . . . . . . . . . . 273
DMA Synchronization Register . . . . . . . . . . 274
DMA Channel registers . . . . . . . . . . . . . . . . 274
DMA Channel Source Address Registers . . 274
DMA Channel Destination Address registers 275
DMA Channel Linked List Item registers . . . 275
DMA channel control registers . . . . . . . . . . . 276
Channel Configuration registers . . . . . . . . . 278
DMA controller functional description . . . . . . 282
AHB slave interface . . . . . . . . . . . . . . . . . . . 282
Control Register (CTRL) . . . . . . . . . . . . . . . . 299
Power Enable Register (PWREN) . . . . . . . . 301
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
16.7.1.2
16.7.1.3
16.7.1.4
16.7.1.5
16.7.1.6
16.7.1.6.1 Bus and transfer widths . . . . . . . . . . . . . . . . 283
16.7.1.6.2 Endian behavior. . . . . . . . . . . . . . . . . . . . . . 283
16.7.1.6.3 Error conditions . . . . . . . . . . . . . . . . . . . . . . 285
16.7.1.7
16.7.1.8
16.7.1.9
16.8
16.8.1
16.8.1.1
16.8.1.2
16.8.1.3
16.8.1.4
16.8.1.5
16.8.1.6
16.8.1.7
16.8.2
16.8.2.1
16.8.2.2
16.8.2.3
16.8.3
16.8.3.1
16.8.4
16.8.4.1
16.8.5
16.8.5.1
16.8.5.1.1 Programming the DMA controller for
16.8.5.1.2 Example of scatter/gather DMA. . . . . . . . . . 292
17.4
17.5
17.6
18.6.3
18.6.4
18.6.5
18.6.6
18.6.7
18.6.8
18.6.9
18.6.10
18.6.11
Using the DMA controller . . . . . . . . . . . . . . . 286
General description . . . . . . . . . . . . . . . . . . . 294
Pin description . . . . . . . . . . . . . . . . . . . . . . . 295
SPIFI API calls . . . . . . . . . . . . . . . . . . . . . . . . 295
Control logic and register bank . . . . . . . . . . 282
DMA request and response interface . . . . . 282
Channel logic and channel register bank. . . 282
Interrupt request. . . . . . . . . . . . . . . . . . . . . . 282
AHB master interface. . . . . . . . . . . . . . . . . . 283
Channel hardware . . . . . . . . . . . . . . . . . . . . 285
DMA request priority . . . . . . . . . . . . . . . . . . 285
Interrupt generation . . . . . . . . . . . . . . . . . . . 285
Programming the DMA controller. . . . . . . . . 286
Enabling the DMA controller . . . . . . . . . . . . 286
Disabling the DMA controller . . . . . . . . . . . . 286
Enabling a DMA channel . . . . . . . . . . . . . . . 286
Disabling a DMA channel. . . . . . . . . . . . . . . 286
Disabling a DMA channel and losing data in the
FIFO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Disabling the DMA channel without losing data in
the FIFO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Setting up a new DMA transfer . . . . . . . . . . 286
Halting a DMA channel . . . . . . . . . . . . . . . . 287
Programming a DMA channel . . . . . . . . . . . 287
Flow control . . . . . . . . . . . . . . . . . . . . . . . . . 287
Peripheral-to-memory or memory-to-peripheral
DMA flow . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Peripheral-to-peripheral DMA flow. . . . . . . . 288
Memory-to-memory DMA flow . . . . . . . . . . . 289
Interrupt requests . . . . . . . . . . . . . . . . . . . . . 290
Hardware interrupt sequence flow . . . . . . . . 290
Address generation . . . . . . . . . . . . . . . . . . . 290
Word-aligned transfers across a boundary . 290
Scatter/gather . . . . . . . . . . . . . . . . . . . . . . . 291
Linked list items . . . . . . . . . . . . . . . . . . . . . . 291
scatter/gather DMA . . . . . . . . . . . . . . . . . . . 291
Clock Divider Register (CLKDIV) . . . . . . . . . 302
SD Clock Source Register (CLKSRC) . . . . . 302
Clock Enable Register (CLKENA) . . . . . . . . 303
Time-out Register (TMOUT) . . . . . . . . . . . . 303
Card Type Register (CTYPE). . . . . . . . . . . . 304
Block Size Register (BLKSIZ) . . . . . . . . . . . 304
Byte Count Register (BYTCNT) . . . . . . . . . . 304
Interrupt Mask Register (INTMASK) . . . . . . 304
Command Argument Register (CMDARG) . 305
Chapter 43: Supplementary information
UM10430
© NXP B.V. 2011. All rights reserved.
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