LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 245

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

15.1 How to read this chapter
Table 165. GPIO pins available
15.2 Basic configuration
<Document ID>
User manual
GPIO Port 0
GPIO Port 1
GPIO Port 2
GPIO Port 3
GPIO Port 4
GPIO Port 5
GPIO Port 6
GPIO Port 7
LBGA256
GPIO0[15:0]
GPIO1[15:0]
GPIO2[15:0]
GPIO3[15:0]
GPIO4[15:0]
GPIO5[26:0]
GPIO6[30:0]
GPIO7[25:0]
Remark: This chapter describes the GPIO of the LPC18xx Rev ‘A’ parts. For the GPIO
block of the LPC18xx Rev ‘-’ parts, see
All GPIO register bit descriptions refer to up to 31 pins on each GPIO port. Depending on
the package type, not all pins are available, and the corresponding bits in the GPIO
registers are reserved (see
The GPIO blocks share a common clock and reset connection and are configured as
follows:
Table 166. GPIO clocking and power control
GPIO, GPIO pin interrupt, GPIO group0
interrupt, GPIO group1 interrupt
•
•
•
•
•
UM10430
Chapter 15: LPC18xx GPIO
Rev. 00.13 — 20 July 2011
See
The GPIO is reset by a GPIO_RST (reset #28).
All GPIO pins are set to input by default.
For the pin interrupts, select up to 8 external interrupt pins from all GPIO port pins in
the SCU (see
NVIC (see
The GPIO group interrupts must be enabled in the NVIC (see
Table 166
TFBGA180
GPIO0[15:0]
GPIO1[15:0]
GPIO2[15:0]
GPIO3[15:0]
GPIO4[15:0]
GPIO5[26:0]
GPIO6[30:25]
GPIO7[4:0]
Table
All information provided in this document is subject to legal disclaimers.
Table 130
for clocking and power control.
13).
Rev. 00.13 — 20 July 2011
TFBGA100
GPIO0[4:0];
GPIO0[15:6]
GPIO1[15:0]
-
GPIO3[1:0];
GPIO3[5:3];
GPIO3[7]
-
GPIO5[11:0]
-
-
Table
and
Table
165).
131). The pin interrupts must be enabled in the
Section
LQFP208
GPIO0[15:0]
GPIO1[15:0]
GPIO2[15:0]
GPIO3[15:0]
GPIO4[15:0]
GPIO5[26:0]
GPIO6[30:0]
GPIO7[25:0]
Base clock
BASE_M3_CLK
42.8.
LQFP144
GPIO0[15:0]
GPIO1[15:0]
GPIO2[15:0]
GPIO3[15:0]
GPIO4[11]
GPIO5[16:0];
GPIO5[18]
-
-
Branch clock
CLK_M3_GPIO
Table
© NXP B.V. 2011. All rights reserved.
13).
LQFP100
GPIO0[4:0];
GPIO0[15:6]
GPIO1[15:0]
-
GPIO3[1:0];
GPIO3[5:3];
GPIO3[7]
-
GPIO5[11:0]
-
-
User manual
Maximum
frequency
150 MHz
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