LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 404

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
20.8.3.1.1 Port reset
20.8.1.9 Multiple Transaction Translators
20.8.2.1 USBMODE register
20.8.2.2 Non-Zero Fields the register file
20.8.2.3 SOF interrupt
20.8.3.1 Discovery
20.8.2 Device operation
20.8.3 Miscellaneous variations from EHCI
The maximum number of embedded Transaction Translators that is currently supported is
one as indicated by the N_TT field in the HCSPARAMS – Host Control Structural
Parameters register.
The co-existence of a device operational controller within the host controller has little
effect on EHCI compatibility for host operation except as noted in this section.
Given that the dual-role controller is initialized in neither host nor device mode, the
USBMODE register must be programmed for host operation before the EHCI host
controller driver can begin EHCI host operations.
operational register have use in device mode, the following must be adhered to:
This SOF Interrupt used for device mode is shared as a free running 125us interrupt for
host mode. EHCI does not specify this interrupt but it has been added for convenience
and as a potential software time base. See USBSTS
(Section
The port connect methods specified by EHCI require setting the port reset bit in the
PORTSCx register for a duration of 10 ms. Due to the complexity required to support the
attachment of devices that are not high speed there are counter already present in the
Some of the reserved fields and reserved addresses in the capability registers and
•
•
– Complete-split transaction searching:
operation registers should always be written to zero. This is an EHCI requirement of
the device controller driver that must be adhered to.
Read operations by the host controller must properly mask EHCI reserved fields
(some of which are device fields) because fields that are used exclusive for device are
undefined in host mode.
Write operations to all EHCI reserved fields (some of which are device fields) with the
keeping the pipeline full puts no constraint on the number of periodic transactions
that can be scheduled in a frame and the only limit becomes the flight time of the
packets on the bus.
There is no data schedule mechanism for these transactions other than
micro-frame pipeline. The embedded TT assumes the number of packets
scheduled in a frame does not exceed the frame duration (1 ms) or else undefined
behavior may result.
20.6.5) registers.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
(Section
20.6.4) and USBINTR
UM10430
© NXP B.V. 2011. All rights reserved.
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