LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 915

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
40.7 Code Read Protection (CRP)
<Document ID>
User manual
Code Read Protection is a mechanism that allows user to enable different levels of
security in the system so that access to the on-chip flash and use of the ISP can be
restricted. When needed, CRP is invoked by programming a specific pattern in flash
location at 0x000002FC. IAP commands are not affected by the code read protection.
Important: Any CRP change becomes effective only after the device has gone
through a power cycle.
Table 841. Code Read Protection options
Name Pattern
CRP1 0x12345678
CRP2 0x87654321
CRP3 0x43218765
programmed in
0x000002FC
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Description
Access to chip via the JTAG pins is disabled. This mode allows partial
flash update using the following ISP commands and restrictions:
This mode is useful when CRP is required and flash field updates are
needed but all sectors can not be erased. The compare command is
disabled, so in the case of partial flash updates the secondary loader
should implement a checksum mechanism to verify the integrity of the
flash.
This is similar to CRP1 with the following additions:
This is similar to CRP2, but ISP entry by pulling P2_7 LOW is disabled
if a valid user code is present in flash sector 0.
This mode effectively disables ISP override using the P2_7 pin. It is up
to the user’s application to provide for flash updates by using IAP calls
or by invoking ISP with UART0.
Caution: If CRP3 is selected, no future factory testing can be
performed on the device.
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Because the ISP code uses SRAM, The Write to RAM command
can not access SRAM below 0x1000 0200, see
Read Memory command: disabled.
Copy RAM to Flash command: cannot write to Sector 0.
Go command: disabled.
Erase sector(s) command: can erase any individual sector except
sector 0 only, or can erase all sectors at once.
Compare command: disabled
Write to RAM command: disabled.
Copy RAM to Flash: disabled.
Erase command: only allows erase of all sectors.
Chapter 40: LPC18xx flash programming interface
UM10430
© NXP B.V. 2011. All rights reserved.
Section
915 of 1164
40.4.2.7.