LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 986

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
42.4.6.3.1 PLL0 status register
42.4.6.3.2 PLL0 control register
42.4.6.3 PLL0 (for USB0) registers
[1]
The PLL0 provides a dedicated clock to the High-speed USB0 interface.
See
Table 933. PLL0_STAT register (PLL0_STAT, address 0x4005 001C) bit description
Table 934. PLL0_CTRL register (PLL0_CTRL, address 0x4005 0020) bit description
Bit
0
1
31:2
Bit
0
1
2
3
4
5
6
7
8
9
10
11
23:12
Do not change the BYPASS and ENABLE bits in one write-action: this will result in unstable device
operation!
Section 42.4.7.4.5
Symbol
PD
BYPASS
DIRECTI
DIRECTO
CLKEN
-
FRM
-
-
-
-
AUTOBLOCK
-
Symbol
LOCK
FR
-
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Description
PLL0 lock indicator
PLL0 free running indicator
Reserved
for instructions on how to set up the PLL0.
Value
0
1
0
1
0
1
Description
PLL0 power down
PLL0 enabled
PLL0 powered down
Input clock bypass control
CCO clock sent to post-dividers. Use this
in normal operation.
PLL0 input clock sent to post-dividers
(default).
PLL0 direct input
PLL0 direct output
PLL0 clock enable
Reserved
Free running mode
Reserved
Reserved. Reads as zero. Do not write
one to this register.
Reserved. Reads as zero. Do not write
one to this register.
Reserved. Reads as zero. Do not write
one to this register.
Block clock automatically during frequency
change
Autoblocking disabled
Autoblocking enabled
Reserved
Chapter 42: Appendix
UM10430
Reset
value
0
0
© NXP B.V. 2011. All rights reserved.
0
0
0
0
Reset
value
1
1
-
0
0
0
0
0
-
986 of 1164
R
R
-
Access
Access
R/W
R/W
R/W
R/W
R/W
-
R/W
R/W
R/W
R/W
R/W
R/W
-